Merge branch 'remotes/lorenzo/pci/tegra'

- Revert tegra RAW fixup that caused a regression (Nicolas Chauvet)

- Remove PLL power supplies from tegra driver and DT binding (Thierry
  Reding)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: Remove PLL power supplies
  dt-bindings: pci: tegra: Remove PLL power supplies
  PCI: tegra: Revert tegra124 raw_violation_fixup

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 7939bca..d099f34 100644 (file)
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -112,28 +112,16 @@ Power supplies for Tegra124:
 - Required:
   - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
   - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
-  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
-    supply 1.05 V.
   - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
     Must supply 3.3 V.
-  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
-    Must supply 3.3 V.
   - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
     supply 2.8-3.3 V.
-  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
-    supply 1.05 V.
 
 Power supplies for Tegra210:
 - Required:
-  - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
-    supply 1.05 V.
   - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
     clocks. Must supply 1.8 V.
   - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
-  - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
-    supply 1.05 V.
-  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
-    Must supply 3.3 V.
   - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
     supply 1.8 V.
 

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 235b456..e25e661 100644 (file)
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -181,13 +181,6 @@
 
 #define AFI_PEXBIAS_CTRL_0             0x168
 
-#define RP_PRIV_XP_DL          0x00000494
-#define  RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD      (0x1ff << 1)
-
-#define RP_RX_HDR_LIMIT                0x00000e00
-#define  RP_RX_HDR_LIMIT_PW_MASK       (0xff << 8)
-#define  RP_RX_HDR_LIMIT_PW            (0x0e << 8)
-
 #define RP_ECTL_2_R1   0x00000e84
 #define  RP_ECTL_2_R1_RX_CTLE_1C_MASK          0xffff
 
@@ -323,7 +316,6 @@ struct tegra_pcie_soc {
        bool program_uphy;
        bool update_clamp_threshold;
        bool program_deskew_time;
-       bool raw_violation_fixup;
        bool update_fc_timer;
        bool has_cache_bars;
        struct {
@@ -659,23 +651,6 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
                writel(value, port->base + RP_VEND_CTL0);
        }
 
-       /* Fixup for read after write violation. */
-       if (soc->raw_violation_fixup) {
-               value = readl(port->base + RP_RX_HDR_LIMIT);
-               value &= ~RP_RX_HDR_LIMIT_PW_MASK;
-               value |= RP_RX_HDR_LIMIT_PW;
-               writel(value, port->base + RP_RX_HDR_LIMIT);
-
-               value = readl(port->base + RP_PRIV_XP_DL);
-               value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
-               writel(value, port->base + RP_PRIV_XP_DL);
-
-               value = readl(port->base + RP_VEND_XP);
-               value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
-               value |= soc->update_fc_threshold;
-               writel(value, port->base + RP_VEND_XP);
-       }
-
        if (soc->update_fc_timer) {
                value = readl(port->base + RP_VEND_XP);
                value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
@@ -2025,7 +2000,7 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
                pcie->supplies[i++].supply = "hvdd-pex";
                pcie->supplies[i++].supply = "vddio-pexctl-aud";
        } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
-               pcie->num_supplies = 6;
+               pcie->num_supplies = 3;
 
                pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
                                              sizeof(*pcie->supplies),
@@ -2033,14 +2008,11 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
                if (!pcie->supplies)
                        return -ENOMEM;
 
-               pcie->supplies[i++].supply = "avdd-pll-uerefe";
                pcie->supplies[i++].supply = "hvddio-pex";
                pcie->supplies[i++].supply = "dvddio-pex";
-               pcie->supplies[i++].supply = "dvdd-pex-pll";
-               pcie->supplies[i++].supply = "hvdd-pex-pll-e";
                pcie->supplies[i++].supply = "vddio-pex-ctl";
        } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
-               pcie->num_supplies = 7;
+               pcie->num_supplies = 4;
 
                pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
                                              sizeof(*pcie->supplies),
@@ -2050,11 +2022,8 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
 
                pcie->supplies[i++].supply = "avddio-pex";
                pcie->supplies[i++].supply = "dvddio-pex";
-               pcie->supplies[i++].supply = "avdd-pex-pll";
                pcie->supplies[i++].supply = "hvdd-pex";
-               pcie->supplies[i++].supply = "hvdd-pex-pll-e";
                pcie->supplies[i++].supply = "vddio-pex-ctl";
-               pcie->supplies[i++].supply = "avdd-pll-erefe";
        } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
                bool need_pexa = false, need_pexb = false;
 
@@ -2416,7 +2385,6 @@ static const struct tegra_pcie_soc tegra20_pcie = {
        .program_uphy = true,
        .update_clamp_threshold = false,
        .program_deskew_time = false,
-       .raw_violation_fixup = false,
        .update_fc_timer = false,
        .has_cache_bars = true,
        .ectl.enable = false,
@@ -2446,7 +2414,6 @@ static const struct tegra_pcie_soc tegra30_pcie = {
        .program_uphy = true,
        .update_clamp_threshold = false,
        .program_deskew_time = false,
-       .raw_violation_fixup = false,
        .update_fc_timer = false,
        .has_cache_bars = false,
        .ectl.enable = false,
@@ -2459,8 +2426,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
        .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
        .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
        .pads_refclk_cfg0 = 0x44ac44ac,
-       /* FC threshold is bit[25:18] */
-       .update_fc_threshold = 0x03fc0000,
        .has_pex_clkreq_en = true,
        .has_pex_bias_ctrl = true,
        .has_intr_prsnt_sense = true,
@@ -2470,7 +2435,6 @@ static const struct tegra_pcie_soc tegra124_pcie = {
        .program_uphy = true,
        .update_clamp_threshold = true,
        .program_deskew_time = false,
-       .raw_violation_fixup = true,
        .update_fc_timer = false,
        .has_cache_bars = false,
        .ectl.enable = false,
@@ -2494,7 +2458,6 @@ static const struct tegra_pcie_soc tegra210_pcie = {
        .program_uphy = true,
        .update_clamp_threshold = true,
        .program_deskew_time = true,
-       .raw_violation_fixup = false,
        .update_fc_timer = true,
        .has_cache_bars = false,
        .ectl = {
@@ -2536,7 +2499,6 @@ static const struct tegra_pcie_soc tegra186_pcie = {
        .program_uphy = false,
        .update_clamp_threshold = false,
        .program_deskew_time = false,
-       .raw_violation_fixup = false,
        .update_fc_timer = false,
        .has_cache_bars = false,
        .ectl.enable = false,