intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s

The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 31f4940..e64ea09 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -501,9 +501,9 @@ isl_tiling_get_info(enum isl_tiling tiling,
       phys_B = isl_extent2d(128, 32);
       break;
 
-   case ISL_TILING_Yf:
-   case ISL_TILING_Ys: {
-      bool is_Ys = tiling == ISL_TILING_Ys;
+   case ISL_TILING_SKL_Yf:
+   case ISL_TILING_SKL_Ys: {
+      bool is_Ys = tiling == ISL_TILING_SKL_Ys;
 
       assert(bs > 0);
       unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys));
@@ -748,8 +748,8 @@ isl_surf_choose_tiling(const struct isl_device *dev,
 
    CHOOSE(ISL_TILING_4);
    CHOOSE(ISL_TILING_64);
-   CHOOSE(ISL_TILING_Ys);
-   CHOOSE(ISL_TILING_Yf);
+   CHOOSE(ISL_TILING_SKL_Ys);
+   CHOOSE(ISL_TILING_SKL_Yf);
    CHOOSE(ISL_TILING_Y0);
    CHOOSE(ISL_TILING_X);
    CHOOSE(ISL_TILING_W);
@@ -1138,7 +1138,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
          assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
                 dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
 
-      if (tiling == ISL_TILING_Ys && info->samples > 1)
+      if (tiling == ISL_TILING_SKL_Ys && info->samples > 1)
          isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
 
       switch (msaa_layout) {
@@ -1866,8 +1866,8 @@ _isl_notify_failure(const struct isl_surf_init_info *surf_info,
             PRINT_TILING(W,              "W"),
             PRINT_TILING(X,              "X"),
             PRINT_TILING(Y0,             "Y0"),
-            PRINT_TILING(Yf,             "Yf"),
-            PRINT_TILING(Ys,             "Ys"),
+            PRINT_TILING(SKL_Yf,         "skl-Yf"),
+            PRINT_TILING(SKL_Ys,         "skl-Ys"),
             PRINT_TILING(4,              "4"),
             PRINT_TILING(64,             "64"),
             PRINT_TILING(HIZ,            "hiz"),
@@ -3741,8 +3741,8 @@ isl_tiling_to_name(enum isl_tiling tiling)
       [ISL_TILING_W]         = "W",
       [ISL_TILING_X]         = "X",
       [ISL_TILING_Y0]        = "Y0",
-      [ISL_TILING_Yf]        = "Yf",
-      [ISL_TILING_Ys]        = "Ys",
+      [ISL_TILING_SKL_Yf]    = "SKL-Yf",
+      [ISL_TILING_SKL_Ys]    = "SKL-Ys",
       [ISL_TILING_4]         = "4",
       [ISL_TILING_64]        = "64",
       [ISL_TILING_HIZ]       = "hiz",

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 928c70b..b8fa41a 100644 (file)
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -576,8 +576,8 @@ enum isl_tiling {
    ISL_TILING_W, /**< W tiling */
    ISL_TILING_X, /**< X tiling */
    ISL_TILING_Y0, /**< Legacy Y tiling */
-   ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
-   ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
+   ISL_TILING_SKL_Yf, /**< Standard 4K tiling. The 'f' means "four". */
+   ISL_TILING_SKL_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
    ISL_TILING_4,  /**< 4K tiling. */
    ISL_TILING_64,  /**< 64K tiling.*/
    ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
@@ -594,8 +594,8 @@ typedef uint32_t isl_tiling_flags_t;
 #define ISL_TILING_W_BIT                  (1u << ISL_TILING_W)
 #define ISL_TILING_X_BIT                  (1u << ISL_TILING_X)
 #define ISL_TILING_Y0_BIT                 (1u << ISL_TILING_Y0)
-#define ISL_TILING_Yf_BIT                 (1u << ISL_TILING_Yf)
-#define ISL_TILING_Ys_BIT                 (1u << ISL_TILING_Ys)
+#define ISL_TILING_SKL_Yf_BIT             (1u << ISL_TILING_SKL_Yf)
+#define ISL_TILING_SKL_Ys_BIT             (1u << ISL_TILING_SKL_Ys)
 #define ISL_TILING_4_BIT                  (1u << ISL_TILING_4)
 #define ISL_TILING_64_BIT                 (1u << ISL_TILING_64)
 #define ISL_TILING_HIZ_BIT                (1u << ISL_TILING_HIZ)
@@ -606,12 +606,12 @@ typedef uint32_t isl_tiling_flags_t;
 
 /** Any Y tiling, including legacy Y tiling. */
 #define ISL_TILING_ANY_Y_MASK             (ISL_TILING_Y0_BIT | \
-                                           ISL_TILING_Yf_BIT | \
-                                           ISL_TILING_Ys_BIT)
+                                           ISL_TILING_SKL_Yf_BIT | \
+                                           ISL_TILING_SKL_Ys_BIT)
 
 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
-#define ISL_TILING_STD_Y_MASK             (ISL_TILING_Yf_BIT | \
-                                           ISL_TILING_Ys_BIT)
+#define ISL_TILING_STD_Y_MASK             (ISL_TILING_SKL_Yf_BIT | \
+                                           ISL_TILING_SKL_Ys_BIT)
 /** @} */
 
 /**

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index ea52dee..aa68df9 100644 (file)
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -47,8 +47,8 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
       return I915_TILING_Y;
 
    case ISL_TILING_W:
-   case ISL_TILING_Yf:
-   case ISL_TILING_Ys:
+   case ISL_TILING_SKL_Yf:
+   case ISL_TILING_SKL_Ys:
    case ISL_TILING_4:
    case ISL_TILING_64:
    case ISL_TILING_GFX12_CCS:

diff --git a/src/intel/isl/isl_gfx7.c b/src/intel/isl/isl_gfx7.c
index 45b8bf2..1ef6381 100644 (file)
--- a/src/intel/isl/isl_gfx7.c
+++ b/src/intel/isl/isl_gfx7.c
@@ -217,8 +217,8 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
    /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
     * them yet.
     */
-   *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */
-   *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */
+   *flags &= ~ISL_TILING_SKL_Yf_BIT; /* FINISHME[SKL]: Support Yf */
+   *flags &= ~ISL_TILING_SKL_Ys_BIT; /* FINISHME[SKL]: Support Ys */
 
    if (isl_surf_usage_is_depth(info->usage)) {
       /* Depth requires Y. */
@@ -250,7 +250,7 @@ isl_gfx6_filter_tiling(const struct isl_device *dev,
           * completeness.
           */
          *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
-                    ISL_TILING_Y0_BIT | ISL_TILING_Yf_BIT);
+                    ISL_TILING_Y0_BIT | ISL_TILING_SKL_Yf_BIT);
       } else {
          /* Before Skylake, the display engine does not accept Y */
          *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);

diff --git a/src/intel/isl/isl_gfx9.c b/src/intel/isl/isl_gfx9.c
index c5674ec..8b99c7e 100644 (file)
--- a/src/intel/isl/isl_gfx9.c
+++ b/src/intel/isl/isl_gfx9.c
@@ -41,7 +41,7 @@ gfx9_calc_std_image_alignment_sa(const struct isl_device *dev,
    assert(isl_tiling_is_std_y(tiling));
 
    const uint32_t bpb = fmtl->bpb;
-   const uint32_t is_Ys = tiling == ISL_TILING_Ys;
+   const uint32_t is_Ys = tiling == ISL_TILING_SKL_Ys;
 
    switch (info->dim) {
    case ISL_SURF_DIM_1D:

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 203d78c..613ab98 100644 (file)
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -49,8 +49,8 @@ static const uint8_t isl_encode_tiling[] = {
    [ISL_TILING_64]      = TILE64,
 #else
    [ISL_TILING_Y0]      = YMAJOR,
-   [ISL_TILING_Yf]      = YMAJOR,
-   [ISL_TILING_Ys]      = YMAJOR,
+   [ISL_TILING_SKL_Yf]  = YMAJOR,
+   [ISL_TILING_SKL_Ys]  = YMAJOR,
 #endif
 #if GFX_VER <= 11
    [ISL_TILING_W]       = WMAJOR,