.reg = 0x7b060,
.shift = 0,
.width = 2,
+ .safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
- .ops = &clk_regmap_mux_closest_ops,
+ .ops = &clk_regmap_mux_safe_ops,
},
},
};
.reg = 0x9d064,
.shift = 0,
.width = 2,
+ .safe_src_parent = P_BI_TCXO,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
- .ops = &clk_regmap_mux_closest_ops,
+ .ops = &clk_regmap_mux_safe_ops,
},
},
};