x86: Support pci bus scan in the early phase
authorBin Meng <bmeng.cn@gmail.com>
Tue, 30 Dec 2014 14:53:20 +0000 (22:53 +0800)
committerSimon Glass <sjg@chromium.org>
Tue, 13 Jan 2015 01:03:41 +0000 (17:03 -0800)
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/pci.c

index 404fbb6..1eee08b 100644 (file)
@@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
        board_pci_setup_hose(hose);
        pci_setup_type1(hose);
+       hose->last_busno = pci_hose_scan(hose);
        gd->arch.hose = hose;
        *hosep = hose;