riscv: dts: microchip: reduce the fic3 clock rate

For the v2022.09 release of the reference design, the fic3 clock rate
been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed
significantly more quickly by customers who chose to build the
reference design themselves.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 35030ea330ee19e04ffd8d1cfef57a10eae64ef0..b6bfe177ccb28a303868401a27b4f4cc86c4f62f 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -29,7 +29,7 @@
        fabric_clk3: fabric-clk3 {
                compatible = "fixed-clock";
                #clock-cells = <0>;
-               clock-frequency = <62500000>;
+               clock-frequency = <50000000>;
        };
 
        fabric_clk1: fabric-clk1 {