radv: initialize FMASK for images in fully expanded mode

The value depends on the number of samples.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c61310f..f4dbab8 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4351,6 +4351,27 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
        state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
 }
 
+void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
+                          struct radv_image *image)
+{
+       struct radv_cmd_state *state = &cmd_buffer->state;
+       static const uint32_t fmask_clear_values[4] = {
+               0x00000000,
+               0x02020202,
+               0xE4E4E4E4,
+               0x76543210
+       };
+       uint32_t log2_samples = util_logbase2(image->info.samples);
+       uint32_t value = fmask_clear_values[log2_samples];
+
+       state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
+                            RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
+       state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
+
+       state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+}
+
 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
                         struct radv_image *image, uint32_t value)
 {
@@ -4386,6 +4407,10 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
                radv_initialise_cmask(cmd_buffer, image, value);
        }
 
+       if (radv_image_has_fmask(image)) {
+               radv_initialize_fmask(cmd_buffer, image);
+       }
+
        if (radv_image_has_dcc(image)) {
                uint32_t value = 0xffffffffu; /* Fully expanded mode. */
                bool need_decompress_pass = false;

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index f8d48f4..22f7ae7 100644 (file)
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -201,6 +201,8 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
 
 uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
                          struct radv_image *image, uint32_t value);
+uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
+                         struct radv_image *image, uint32_t value);
 uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
                        struct radv_image *image, uint32_t value);
 

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 7a364ec..cd6a90e 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1296,6 +1296,15 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 }
 
 uint32_t
+radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
+                struct radv_image *image, uint32_t value)
+{
+       return radv_fill_buffer(cmd_buffer, image->bo,
+                               image->offset + image->fmask.offset,
+                               image->fmask.size, value);
+}
+
+uint32_t
 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
               struct radv_image *image, uint32_t value)
 {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 9a9cd5f..5204e87 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1895,6 +1895,9 @@ void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
                         struct radv_image *image, uint32_t value);
 
+void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
+                          struct radv_image *image);
+
 struct radv_fence {
        struct radeon_winsys_fence *fence;
        struct wsi_fence *fence_wsi;