clk: samsung: remove s3c24xx specific pll bits

With the s3c24xx clk driver gone, the portions of the pll driver
for it can also be removed.

Suggested-by: Chanwoo Choi <cwchoi00@gmail.com>
Link: https://lore.kernel.org/linux-arm-kernel/0e0eff12-d8ea-72e9-d135-4259dda9a750@gmail.com/
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0ff2893..df78123 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -941,169 +941,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = {
 };
 
 /*
- * PLL Clock Type of S3C24XX before S3C2443
- */
-
-#define PLLS3C2410_MDIV_MASK           (0xff)
-#define PLLS3C2410_PDIV_MASK           (0x1f)
-#define PLLS3C2410_SDIV_MASK           (0x3)
-#define PLLS3C2410_MDIV_SHIFT          (12)
-#define PLLS3C2410_PDIV_SHIFT          (4)
-#define PLLS3C2410_SDIV_SHIFT          (0)
-
-#define PLLS3C2410_ENABLE_REG_OFFSET   0x10
-
-static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
-                                       unsigned long parent_rate)
-{
-       struct samsung_clk_pll *pll = to_clk_pll(hw);
-       u32 pll_con, mdiv, pdiv, sdiv;
-       u64 fvco = parent_rate;
-
-       pll_con = readl_relaxed(pll->con_reg);
-       mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
-       pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
-       sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
-
-       fvco *= (mdiv + 8);
-       do_div(fvco, (pdiv + 2) << sdiv);
-
-       return (unsigned int)fvco;
-}
-
-static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
-                                       unsigned long parent_rate)
-{
-       struct samsung_clk_pll *pll = to_clk_pll(hw);
-       u32 pll_con, mdiv, pdiv, sdiv;
-       u64 fvco = parent_rate;
-
-       pll_con = readl_relaxed(pll->con_reg);
-       mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
-       pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
-       sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
-
-       fvco *= (2 * (mdiv + 8));
-       do_div(fvco, (pdiv + 2) << sdiv);
-
-       return (unsigned int)fvco;
-}
-
-static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
-                                       unsigned long prate)
-{
-       struct samsung_clk_pll *pll = to_clk_pll(hw);
-       const struct samsung_pll_rate_table *rate;
-       u32 tmp;
-
-       /* Get required rate settings from table */
-       rate = samsung_get_pll_settings(pll, drate);
-       if (!rate) {
-               pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-                       drate, clk_hw_get_name(hw));
-               return -EINVAL;
-       }
-
-       tmp = readl_relaxed(pll->con_reg);
-
-       /* Change PLL PMS values */
-       tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
-                       (PLLS3C2410_PDIV_MASK << PLLS3C2410_PDIV_SHIFT) |
-                       (PLLS3C2410_SDIV_MASK << PLLS3C2410_SDIV_SHIFT));
-       tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
-                       (rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
-                       (rate->sdiv << PLLS3C2410_SDIV_SHIFT);
-       writel_relaxed(tmp, pll->con_reg);
-
-       /* Time to settle according to the manual */
-       udelay(300);
-
-       return 0;
-}
-
-static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
-{
-       struct samsung_clk_pll *pll = to_clk_pll(hw);
-       u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
-       u32 pll_en_orig = pll_en;
-
-       if (enable)
-               pll_en &= ~BIT(bit);
-       else
-               pll_en |= BIT(bit);
-
-       writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
-
-       /* if we started the UPLL, then allow to settle */
-       if (enable && (pll_en_orig & BIT(bit)))
-               udelay(300);
-
-       return 0;
-}
-
-static int samsung_s3c2410_mpll_enable(struct clk_hw *hw)
-{
-       return samsung_s3c2410_pll_enable(hw, 5, true);
-}
-
-static void samsung_s3c2410_mpll_disable(struct clk_hw *hw)
-{
-       samsung_s3c2410_pll_enable(hw, 5, false);
-}
-
-static int samsung_s3c2410_upll_enable(struct clk_hw *hw)
-{
-       return samsung_s3c2410_pll_enable(hw, 7, true);
-}
-
-static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
-{
-       samsung_s3c2410_pll_enable(hw, 7, false);
-}
-
-static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
-       .recalc_rate = samsung_s3c2410_pll_recalc_rate,
-       .enable = samsung_s3c2410_mpll_enable,
-       .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
-       .recalc_rate = samsung_s3c2410_pll_recalc_rate,
-       .enable = samsung_s3c2410_upll_enable,
-       .disable = samsung_s3c2410_upll_disable,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
-       .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
-       .enable = samsung_s3c2410_mpll_enable,
-       .disable = samsung_s3c2410_mpll_disable,
-};
-
-static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
-       .recalc_rate = samsung_s3c2410_pll_recalc_rate,
-       .enable = samsung_s3c2410_mpll_enable,
-       .disable = samsung_s3c2410_mpll_disable,
-       .round_rate = samsung_pll_round_rate,
-       .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
-       .recalc_rate = samsung_s3c2410_pll_recalc_rate,
-       .enable = samsung_s3c2410_upll_enable,
-       .disable = samsung_s3c2410_upll_disable,
-       .round_rate = samsung_pll_round_rate,
-       .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
-       .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
-       .enable = samsung_s3c2410_mpll_enable,
-       .disable = samsung_s3c2410_mpll_disable,
-       .round_rate = samsung_pll_round_rate,
-       .set_rate = samsung_s3c2410_pll_set_rate,
-};
-
-/*
  * PLL2550x Clock Type
  */
 
@@ -1530,24 +1367,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
                else
                        init.ops = &samsung_pll46xx_clk_ops;
                break;
-       case pll_s3c2410_mpll:
-               if (!pll->rate_table)
-                       init.ops = &samsung_s3c2410_mpll_clk_min_ops;
-               else
-                       init.ops = &samsung_s3c2410_mpll_clk_ops;
-               break;
-       case pll_s3c2410_upll:
-               if (!pll->rate_table)
-                       init.ops = &samsung_s3c2410_upll_clk_min_ops;
-               else
-                       init.ops = &samsung_s3c2410_upll_clk_ops;
-               break;
-       case pll_s3c2440_mpll:
-               if (!pll->rate_table)
-                       init.ops = &samsung_s3c2440_mpll_clk_min_ops;
-               else
-                       init.ops = &samsung_s3c2440_mpll_clk_ops;
-               break;
        case pll_2550x:
                init.ops = &samsung_pll2550x_clk_ops;
                break;

diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a9892c2..5d5a58d 100644 (file)
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -25,9 +25,6 @@ enum samsung_pll_type {
        pll_6552,
        pll_6552_s3c2416,
        pll_6553,
-       pll_s3c2410_mpll,
-       pll_s3c2410_upll,
-       pll_s3c2440_mpll,
        pll_2550x,
        pll_2550xx,
        pll_2650x,
@@ -56,24 +53,6 @@ enum samsung_pll_type {
                .sdiv   =       (_s),                           \
        }
 
-#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s)         \
-       {                                                       \
-               .rate   =       PLL_VALID_RATE(_fin, _rate,     \
-                               _m + 8, _p + 2, _s, 0, 16),     \
-               .mdiv   =       (_m),                           \
-               .pdiv   =       (_p),                           \
-               .sdiv   =       (_s),                           \
-       }
-
-#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s)         \
-       {                                                       \
-               .rate   =       PLL_VALID_RATE(_fin, _rate,     \
-                               2 * (_m + 8), _p + 2, _s, 0, 16), \
-               .mdiv   =       (_m),                           \
-               .pdiv   =       (_p),                           \
-               .sdiv   =       (_s),                           \
-       }
-
 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)             \
        {                                                       \
                .rate   =       PLL_VALID_RATE(_fin, _rate,     \