x86: coreboot: Sync up timestamp codes

Add new timestamp codes that are present in coreboot, so that we can decode
these in U-Boot.

At present TS_U_BOOT_START_KERNEL is used twice. It should only be used
just before jumping to Linux, so update the other call site to use
TS_START_KERNEL.

Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index dec0c14..3172814 100644 (file)
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -22,14 +22,24 @@ struct timestamp_table {
 } __packed;
 
 enum timestamp_id {
-       /* coreboot specific timestamp IDs */
+       /* coreboot-specific timestamp IDs */
        TS_START_ROMSTAGE = 1,
        TS_BEFORE_INITRAM = 2,
        TS_AFTER_INITRAM = 3,
        TS_END_ROMSTAGE = 4,
+       TS_START_VBOOT = 5,
+       TS_END_VBOOT = 6,
        TS_START_COPYRAM = 8,
        TS_END_COPYRAM = 9,
        TS_START_RAMSTAGE = 10,
+       TS_START_BOOTBLOCK = 11,
+       TS_END_BOOTBLOCK = 12,
+       TS_START_COPYROM = 13,
+       TS_END_COPYROM = 14,
+       TS_START_ULZMA = 15,
+       TS_END_ULZMA = 16,
+       TS_START_ULZ4F = 17,
+       TS_END_ULZ4F = 18,
        TS_DEVICE_ENUMERATE = 30,
        TS_DEVICE_CONFIGURE = 40,
        TS_DEVICE_ENABLE = 50,
@@ -37,12 +47,64 @@ enum timestamp_id {
        TS_DEVICE_DONE = 70,
        TS_CBMEM_POST = 75,
        TS_WRITE_TABLES = 80,
+       TS_FINALIZE_CHIPS = 85,
        TS_LOAD_PAYLOAD = 90,
        TS_ACPI_WAKE_JUMP = 98,
        TS_SELFBOOT_JUMP = 99,
 
+       /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
+       TS_START_COPYVER = 501,
+       TS_END_COPYVER = 502,
+       TS_START_TPMINIT = 503,
+       TS_END_TPMINIT = 504,
+       TS_START_VERIFY_SLOT = 505,
+       TS_END_VERIFY_SLOT = 506,
+       TS_START_HASH_BODY = 507,
+       TS_DONE_LOADING = 508,
+       TS_DONE_HASHING = 509,
+       TS_END_HASH_BODY = 510,
+       TS_START_COPYVPD = 550,
+       TS_END_COPYVPD_RO = 551,
+       TS_END_COPYVPD_RW = 552,
+
+       /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
+       TS_ME_INFORM_DRAM_WAIT = 940,
+       TS_ME_INFORM_DRAM_DONE = 941,
+
+       /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
+       TS_FSP_MEMORY_INIT_START = 950,
+       TS_FSP_MEMORY_INIT_END = 951,
+       TS_FSP_TEMP_RAM_EXIT_START = 952,
+       TS_FSP_TEMP_RAM_EXIT_END = 953,
+       TS_FSP_SILICON_INIT_START = 954,
+       TS_FSP_SILICON_INIT_END = 955,
+       TS_FSP_BEFORE_ENUMERATE = 956,
+       TS_FSP_AFTER_ENUMERATE = 957,
+       TS_FSP_BEFORE_FINALIZE = 958,
+       TS_FSP_AFTER_FINALIZE = 959,
+       TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
+       TS_FSP_AFTER_END_OF_FIRMWARE = 961,
+
+       /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */
+
        /* U-Boot entry IDs start at 1000 */
        TS_U_BOOT_INITTED = 1000, /* This is where U-Boot starts */
+
+       TS_RO_PARAMS_INIT = 1001,
+       TS_RO_VB_INIT = 1002,
+       TS_RO_VB_SELECT_FIRMWARE = 1003,
+       TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004,
+
+       TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010,
+
+       TS_VB_SELECT_AND_LOAD_KERNEL = 1020,
+       TS_VB_EC_VBOOT_DONE = 1030,
+       TS_VB_STORAGE_INIT_DONE = 1040,
+       TS_VB_READ_KERNEL_DONE = 1050,
+       TS_VB_VBOOT_DONE = 1100,
+
+       TS_START_KERNEL = 1101,
+       TS_KERNEL_DECOMPRESSION = 1102,
        TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel */
 };
 

diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index aa5f0bf..733dd71 100644 (file)
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -36,7 +36,7 @@ void bootm_announce_and_cleanup(void)
        printf("\nStarting kernel ...\n\n");
 
 #ifdef CONFIG_SYS_COREBOOT
-       timestamp_add_now(TS_U_BOOT_START_KERNEL);
+       timestamp_add_now(TS_START_KERNEL);
 #endif
        bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 #if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)