drm/exynos: mask alpha bit in the register when output format is XRGB8888

When color format changes YUV to RGB by ipp gsc,
the color of output image seems to come out.

The alpha value should have ignored but bits
in the GSCALER_OUT_CON register do not set to 0xff(masking alpha value)

This patch masks alpha bits in the GSCALER_OUT_CON register
when the userspace decide to use XRGB8888.

Change-Id: I78bf2d8214cbdb10568b3bb4b9af6b9bf28752a5
Signed-off-by: Ingi Kim <ingi2.kim@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index e285ff3..2ab3fbb 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -874,7 +874,7 @@ static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
                cfg |= GSC_OUT_RGB565;
                break;
        case DRM_FORMAT_XRGB8888:
-               cfg |= GSC_OUT_XRGB8888;
+               cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
                break;
        case DRM_FORMAT_BGRX8888:
                cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);