[BZ #2505]

2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>
	[BZ #2505]
	* sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
	Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.

diff --git a/ChangeLog b/ChangeLog
index 7235b2f..d0d3cac 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -10,6 +10,12 @@
        ($(objpfx)iso8859-7jp.stmp): Likewise.
        Reported by S.Çağlar Onur <caglar@uludag.org.tr>.
 
+2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>
+
+       [BZ #2505]
+       * sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
+       Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.
+
 2006-04-03  Andreas Schwab  <schwab@suse.de>
 
        * sysdeps/unix/sysv/linux/powerpc/powerpc32/clone.S: Terminate FDE

diff --git a/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h b/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
index fcc1240..abd019d 100644 (file)
--- a/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
+++ b/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
@@ -110,7 +110,21 @@
 # define __lll_rel_instr       ""
 #else
 # define __lll_acq_instr       "isync"
-# define __lll_rel_instr       "sync"
+# ifdef _ARCH_PWR4
+/*
+ * Newer powerpc64 processors support the new "light weight" sync (lwsync)
+ * So if the build is using -mcpu=[power4,power5,power5+,970] we can
+ * safely use lwsync.
+ */
+#  define __lll_rel_instr      "lwsync"
+# else
+/*
+ * Older powerpc32 processors don't support the new "light weight"
+ * sync (lwsync).  So the only safe option is to use normal sync
+ * for all powerpc32 applications.
+ */
+#  define __lll_rel_instr      "sync"
+# endif
 #endif
 
 /* Set *futex to ID if it is 0, atomically.  Returns the old value */

diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h
index 0f1a723..6fcc669 100644 (file)
--- a/sysdeps/powerpc/powerpc32/bits/atomic.h
+++ b/sysdeps/powerpc/powerpc32/bits/atomic.h
@@ -89,12 +89,27 @@
 # define __arch_atomic_decrement_if_positive_64(mem) \
     ({ abort (); (*mem)--; })
 
+#ifdef _ARCH_PWR4
+/*
+ * Newer powerpc64 processors support the new "light weight" sync (lwsync)
+ * So if the build is using -mcpu=[power4,power5,power5+,970] we can
+ * safely use lwsync.
+ */
+# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
+/*
+ * "light weight" sync can also be used for the release barrier.
+ */
+# ifndef UP
+#  define __ARCH_REL_INSTR     "lwsync"
+# endif
+#else
 /*
  * Older powerpc32 processors don't support the new "light weight"
  * sync (lwsync).  So the only safe option is to use normal sync
  * for all powerpc32 applications.
  */
 # define atomic_read_barrier() __asm ("sync" ::: "memory")
+#endif
 
 /*
  * Include the rest of the atomic ops macros which are common to both