SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
+#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
u-boot.cnt: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
endif
-endif
+#endif
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
- select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
- select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
return 0;
}
+#if !CONFIG_IS_ENABLED(SYSRESET)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
scfg_out32(rstcr, val);
#endif
}
+#endif
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
#endif
}
+#ifndef CONFIG_SPL_BUILD
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
{
int i, ret;
fdt_fixup_fman_icids(blob, smmu_ph);
#endif
}
+#endif
SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
- SCFG_SNPCNFGCR_SATAWRSNP);
+ SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
#elif defined(CONFIG_ARCH_LS1012A)
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
- imx6ul-kontron-n631x-s.dtb \
- imx6ull-kontron-n641x-s.dtb
+ imx6ul-kontron-bl.dtb \
+ imx6ull-kontron-bl.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
- imx8mm-kontron-n801x-s.dtb \
- imx8mm-kontron-n801x-s-lvds.dtb \
+ imx8mm-kontron-bl.dtb \
+ imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw7901.dtb \
imx8mm-venice-gw7902.dtb \
imx8mm-venice-gw7903.dtb \
+ imx8mm-venice-gw7904.dtb \
imx8mm-verdin-wifi-dev.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
+ imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
- MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
// SPDX-License-Identifier: GPL-2.0+
&gpio0 {
- gpio-ranges = <&pinctrl 0 0 32>;
+ gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 0 32>;
};
&gpio1 {
- gpio-ranges = <&pinctrl 0 32 31>;
+ gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 32 31>;
};
&gpio2 {
- gpio-ranges = <&pinctrl 0 63 32>;
+ gpio-ranges = <&{/apb@80000000/apbh@80000000/pinctrl@80018000} 0 63 32>;
};
-
status = "disabled";
};
- pinctrl: pinctrl@80018000 {
+ pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b", "jedec,spi-nor";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+
+/ {
+ aliases {
+ spi2 = &ssp3;
+ };
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x08000000>;
+ };
+
+ reg_3v3: regulator-reg-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_5v: regulator-reg-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_fec_3v3: regulator-reg-fec-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clks 53>;
+ assigned-clock-rates = <12000000>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&spi3_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a>;
+ bus-width = <8>;
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&ssp3 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "env0";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition@90000 {
+ label = "env1";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "swupdate";
+ reg = <0x500000 0x800000>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_b>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
};
&ssp3 {
+ num-cs = <2>;
+ spi-max-frequency = <40000000>;
u-boot,dm-spl;
};
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2019
+ * Copyright 2021
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+ or X11
- *
*/
/dts-v1/;
-
-#include "imx28.dtsi"
+#include "imx28-lwe.dtsi"
/ {
- model = "Liebherr (LWE) XEA i.MX28 Board";
- compatible = "lwe,xea", "fsl,imx28";
-
- aliases {
- spi3 = &ssp3;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x10000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_fec_3v3: regulator-fec-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "fec-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-boot-on;
- };
-
- reg_usb_5v: regulator-usb-5v {
- compatible = "regulator-fixed";
- regulator-name = "usb_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ compatible = "lwn,imx28-xea", "fsl,imx28";
};
-&mac0 {
- phy-mode = "rmii";
+&can0 {
pinctrl-names = "default";
- pinctrl-0 = <&mac0_pins_a>;
- phy-supply = <®_fec_3v3>;
- phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
- phy-reset-duration = <1>;
- phy-reset-post-delay = <1>;
+ pinctrl-0 = <&can1_pins_a>;
status = "okay";
-
- fixed-link {
- speed = <100>;
- full-duplex;
- };
};
-&ssp0 {
- compatible = "fsl,imx28-mmc";
+&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_8bit_pins_a>;
- bus-width = <8>;
- vmmc-supply = <®_3p3v>;
- non-removable;
+ pinctrl-0 = <&i2c1_pins_b>;
status = "okay";
};
-&ssp3 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx28-spi";
+&pinctrl {
pinctrl-names = "default";
- pinctrl-0 = <&spi3_pins_b>;
- status = "okay";
- spi-max-frequency = <40000000>;
- num-cs = <2>;
+ pinctrl-0 = <&hog_pins_a &hog_pins_tiva>;
- flash0: s25fl256s@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
+ hog_pins_a: hog@0 {
reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__GPIO_0_0
+ MX28_PAD_GPMI_D02__GPIO_0_2
+ MX28_PAD_GPMI_D05__GPIO_0_5
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ MX28_PAD_GPMI_RDY0__GPIO_0_20
+ MX28_PAD_GPMI_RDY1__GPIO_0_21
+ MX28_PAD_GPMI_RDY2__GPIO_0_22
+ MX28_PAD_GPMI_RDN__GPIO_0_24
+ MX28_PAD_GPMI_CLE__GPIO_0_27
+ MX28_PAD_LCD_VSYNC__GPIO_1_28
+ MX28_PAD_SSP1_SCK__GPIO_2_12
+ MX28_PAD_SSP1_CMD__GPIO_2_13
+ MX28_PAD_SSP2_SS1__GPIO_2_20
+ MX28_PAD_SSP2_SS2__GPIO_2_21
+ MX28_PAD_LCD_D00__GPIO_1_0
+ MX28_PAD_LCD_D01__GPIO_1_1
+ MX28_PAD_LCD_D02__GPIO_1_2
+ MX28_PAD_LCD_D03__GPIO_1_3
+ MX28_PAD_LCD_D04__GPIO_1_4
+ MX28_PAD_LCD_D05__GPIO_1_5
+ MX28_PAD_LCD_D06__GPIO_1_6
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ hog_pins_tiva: hog@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY3__GPIO_0_23
+ MX28_PAD_GPMI_WRN__GPIO_0_25
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "SPL";
- reg = <0x0 0x10000>;
- read-only;
- };
- partition@10000 {
- label = "u-boot";
- reg = <0x10000 0x70000>;
- read-only;
- };
- partition@80000 {
- label = "uboot-env1";
- reg = <0x80000 0x10000>;
- };
- partition@90000 {
- label = "uboot-env2";
- reg = <0x90000 0x10000>;
- };
- partition@A0000 {
- label = "rescue";
- reg = <0xA0000 0xF40000>;
- };
- partition@FE0000 {
- label = "spl-boot-data1";
- reg = <0xFE0000 0x10000>;
- };
- partition@FF0000 {
- label = "spl-boot-data2";
- reg = <0xFF0000 0x10000>;
- };
- };
+ hog_pins_coding: hog@2 {
+ reg = <2>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D01__GPIO_0_1
+ MX28_PAD_GPMI_D03__GPIO_0_3
+ MX28_PAD_GPMI_D04__GPIO_0_4
+ MX28_PAD_GPMI_D06__GPIO_0_6
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
-&usb0 {
- vbus-supply = <®_usb_5v>;
- status = "okay";
+®_fec_3v3 {
+ gpio = <&gpio0 0 0>;
};
-&usbphy0 {
- status = "okay";
+®_usb_5v {
+ gpio = <&gpio0 2 0>;
+};
+
+&spi2_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ >;
};
status = "disabled";
};
- gpmi: gpmi-nand@8000c000 {
+ gpmi: nand-controller@8000c000 {
compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
interrupt-names = "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
+ assigned-clocks = <&clks 13>;
+ assigned-clock-parents = <&clks 10>;
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
status = "disabled";
fsl,pull-up = <MXS_PULL_DISABLE>;
};
+ usb1_pins_b: usb1@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_PWM2__USB1_OVERCURRENT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
usb0_id_pins_a: usb0id@0 {
reg = <0>;
fsl,pinmux-ids = <
clocks = <&clks 26>;
};
- dcp: dcp@80028000 {
+ dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53 54>;
status = "disabled";
};
- ocotp: ocotp@8002c000 {
+ ocotp: efuse@8002c000 {
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
- etn_switch: switch@800f8000 {
+ eth_switch: switch@800f8000 {
reg = <0x800f8000 0x8000>;
status = "disabled";
};
clocks {
ckil {
- compatible = "fsl,imx-ckil", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
- compatible = "fsl,imx-ckih1", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
- compatible = "fsl,imx-ckih2", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
- compatible = "fsl,imx-osc", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
ports = <&ipu_di0>, <&ipu_di1>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
};
};
- bus@70000000 { /* AIPS1 */
+ aips1: bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x10000000>;
ranges;
- spba@70000000 {
+ spba-bus@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
+ dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
+ dma-names = "rx", "tx";
status = "disabled";
};
};
};
- bus@80000000 { /* AIPS2 */
+ aips2: bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
iim: efuse@83f98000 {
- compatible = "fsl,imx51-iim", "fsl,imx27-iim";
+ compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2016 Beckhoff Automation
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 Beckhoff Automation GmbH & Co. KG
+ * based on imx53-qsb.dts
*/
/dts-v1/;
#include "imx53.dtsi"
-#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
-#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
-#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
-#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
-
/ {
- model = "Beckhoff CX9020-0100 i.MX53";
- compatible = "fsl,imx53-qsb", "fsl,imx53";
+ model = "Beckhoff CX9020 Embedded PC";
+ compatible = "bhf,cx9020", "fsl,imx53";
chosen {
stdout-path = &uart2;
};
-};
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
+ memory@70000000 {
+ device_type = "memory";
+ reg = <0x70000000 0x20000000>,
+ <0xb0000000 0x20000000>;
+ };
+
+ display-0 {
+ #address-cells =<1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display0_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+ };
+
+ dvi-connector {
+ compatible = "dvi-connector";
+ ddc-i2c-bus = <&i2c2>;
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
- imx53-qsb {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
- MX53_PAD_GPIO_8__GPIO1_8 0x80000000
- MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
- MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
- MX53_PAD_GPIO_1__GPIO1_1 0x80000000
- MX53_PAD_GPIO_4__GPIO1_4 0x80000000
- MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
- MX53_PAD_GPIO_16__GPIO7_11 0x80000000
-
- MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
- MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000
- MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000
- MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
- MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000
- MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000
- MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000
- MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000
- MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000
- MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
- MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000
- MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000
- MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000
- MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000
- MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000
- MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000
- MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000
- MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
- MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
- MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
- MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
- MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
- MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
- MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
- MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
- MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4
- MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4
- MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4
- MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4
- MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4
- MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4
- MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4
- MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4
- MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
- MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
- MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
- MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
- MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
- MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
- MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
- MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
- MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4
- MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4
- MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4
- MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4
- MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4
- MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4
- MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4
- MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4
- MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001
- MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001
- MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001
-
- MX53_PAD_EIM_D23__GPIO3_23 0x80000000
-
- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
-
- MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
- MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
-
- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
-
- MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
- MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
- MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
- MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
- MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
- MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
- MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
- MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
- MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
- MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
- MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
- MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
- MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
- MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
- MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
- MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
- MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
- MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
- MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
- MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
- MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
- MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
- MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
- MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
- MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
- MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
- MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
- MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
- MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
- >;
+ dvi-converter {
+ compatible = "ti,tfp410";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr-r {
+ gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
};
- pinctrl_fec0: fec0grp {
- fsl,pins = <
- MX53_PAD_FEC_MDC__FEC_MDC 0x4
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
- >;
+ pwr-g {
+ gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
};
- pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
- >;
+ pwr-b {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
};
- pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <
- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
- >;
+ sd1-b {
+ linux,default-trigger = "mmc0";
+ gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
};
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
- MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
- MX53_PAD_EIM_D28__UART2_RTS 0x1e4
- MX53_PAD_EIM_D29__UART2_CTS 0x1e4
- >;
+ sd2-b {
+ linux,default-trigger = "mmc1";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
};
};
-};
-&uart2 {
- pinctrl-names = "default";
- uart-has-rtscts;
- fsl,dte-mode;
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
+ regulator-3p2v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P2V";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-always-on;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&esdhc1 {
&fec {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
- phy-reset-gpios = <&gpio7 6 0>;
- pinctrl-0 = <&pinctrl_fec0>;
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&ipu_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,dte-mode;
status = "okay";
- fixed-link { /* RMII fixed link to KZ8863 */
- speed = <100>;
- full-duplex;
- };
};
&usbh1 {
+ vbus-supply = <®_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
- dr_mode = "host";
+ dr_mode = "peripheral";
status = "okay";
};
+
+&vpu {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_0__CCM_CLKO 0x1c4
+ MX53_PAD_GPIO_16__I2C3_SDA 0x1c4
+ MX53_PAD_EIM_D22__GPIO3_22 0x1c4
+ MX53_PAD_EIM_D23__GPIO3_23 0x1e4
+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_GPIO_1__ESDHC1_CD 0x1c4
+ MX53_PAD_EIM_D17__GPIO3_17 0x1e4
+ MX53_PAD_GPIO_3__GPIO1_3 0x1c4
+ >;
+ };
+
+ pinctrl_esdhc2: esdhc2grp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ MX53_PAD_GPIO_4__ESDHC2_CD 0x1e4
+ MX53_PAD_EIM_D20__GPIO3_20 0x1e4
+ MX53_PAD_GPIO_8__GPIO1_8 0x1c4
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
+ };
+
+ pinctrl_ipu_disp0: ipudisp0grp {
+ fsl,pins = <
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
+ MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
+ MX53_PAD_EIM_D28__UART2_RTS 0x1e4
+ MX53_PAD_EIM_D29__UART2_CTS 0x1e4
+ >;
+ };
+};
#include "imx53.dtsi"
#include "imx53-pinfunc.h"
+#define IMX_PAD_SION 0x40000000
+
/ {
model = "K+P iMX53";
compatible = "kp,imx53-kp", "fsl,imx53";
/dts-v1/;
#include "imx53-m53.dtsi"
-#include "imx53-m53menlo-u-boot.dtsi"
/ {
model = "MENLO M53 EMBEDDED DEVICE";
compatible = "menlo,m53menlo", "fsl,imx53";
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pinctrl_power_button>;
+ pinctrl-names = "default";
+
+ power-button {
+ label = "Power button";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pinctrl_power_out>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
eth {
label = "EthLedYe";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "none";
+ linux,default-trigger = "netdev";
+ };
+ };
+
+ lvds-decoder {
+ compatible = "ti,ds90cf364a", "lvds-decoder";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_decoder_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_decoder_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
};
panel {
- compatible = "edt,etm070080dh6";
+ compatible = "edt,etm0700g0dh6";
+ pinctrl-0 = <&pinctrl_display_gpio>;
+ pinctrl-names = "default";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {
panel_in: endpoint {
- remote-endpoint = <&lvds0_out>;
+ remote-endpoint = <&lvds_decoder_out>;
};
};
};
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ };
+
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio1 2 0>;
};
};
assigned-clock-rates = <133333334>, <33333334>, <33333334>;
};
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "menlo,m53cpld";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+
+ spidev@1 {
+ compatible = "menlo,m53cpld";
+ spi-max-frequency = <25000000>;
+ reg = <1>;
+ };
+};
+
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
- phy-handle = <ðphy0>;
phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>;
status = "okay";
+};
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
- };
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "TestPin_SV2_3", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "",
+ "", "CPLD_JTAG_TDO", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "CPLD_JTAG_TCK", "KBD_intK",
+ "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]",
+ "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]",
+ "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "",
+ "CPLD_reset", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio7 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "USB-OTG_OverCurrent", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
};
&i2c1 {
imx53-m53evk {
hoggrp {
fsl,pins = <
- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
- MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
- MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
- MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
- MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
- MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
- MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
- MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
- MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
- MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
- MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
- MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
- MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
- MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
+ MX53_PAD_GPIO_19__CCM_CLKO 0x1e4
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4
+ MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4
+ MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4
+ MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4
+ MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4
+ MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4
+ MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4
+ MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4
+ MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4
+ MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4
+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+ MX53_PAD_EIM_D25__GPIO3_25 0x1e4
+ MX53_PAD_EIM_D29__GPIO3_29 0x1e4
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4
+ MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4
+ MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4
+ MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
- MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
- MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
+ MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4
+ MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4
+ >;
+ };
+
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
+ MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
>;
};
pinctrl_display_gpio: display-gpiogrp {
fsl,pins = <
- MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
- MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
+ MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */
+ MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */
+ MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */
+
+ MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
- MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
- MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
- MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
+ MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */
+ MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */
+ MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4
+ MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4
+ MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4
+ MX53_PAD_EIM_RW__GPIO2_26 0xe4
+ MX53_PAD_EIM_LBA__GPIO2_27 0xe4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4
+ MX53_PAD_GPIO_1__GPIO1_1 0x1c4
+ MX53_PAD_GPIO_9__GPIO1_9 0x1e4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
- MX53_PAD_FEC_MDC__FEC_MDC 0x4
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
+ MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4
+ MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
>;
};
>;
};
+ pinctrl_power_button: powerbutgrp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4
+ >;
+ };
+
+ pinctrl_power_out: poweroutgrp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4
+ MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4
>;
};
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4
+ MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_usb: usbgrp {
fsl,pins = <
- MX53_PAD_GPIO_2__GPIO1_2 0x1d5
- MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
+ MX53_PAD_GPIO_2__GPIO1_2 0x1c4
+ MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4
+ MX53_PAD_GPIO_4__GPIO1_4 0x1c4
+ MX53_PAD_GPIO_18__GPIO7_13 0x1c4
>;
};
};
reg = <2>;
lvds0_out: endpoint {
- remote-endpoint = <&panel_in>;
+ remote-endpoint = <&lvds_decoder_in>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ linux,rs485-enabled-at-boot-time;
status = "okay";
};
pinctrl-0 = <&pinctrl_usb>;
vbus-supply = <®_usbh1_vbus>;
phy_type = "utmi";
- dr_mode = "peripheral";
+ dr_mode = "host";
status = "okay";
};
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __DTS_IMX53_PINFUNC_H
#define __DTS_IMX53_PINFUNC_H
-#define IMX_PAD_SION 0x40000000
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0
#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0
#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0
#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0
#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0
#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0
#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0
#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1
+#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0
#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0
#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0
#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0
#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0
#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1
#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1
#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0
#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0
+#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1
#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0
#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2
-// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 General Electric Company
*
clock-frequency = <11289600>;
};
+ achc_24M: achc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
sgtlsound: sound {
compatible = "fsl,imx53-cpuvo-sgtl5000",
"fsl,imx-audio-sgtl5000";
power-supply = <®_3v3_lcd>;
};
- leds {
+ led-controller-1 {
compatible = "pwm-leds";
- alarm-brightness {
+ led-1 {
+ label = "alarm-brightness";
pwms = <&pwm1 0 100000>;
max-brightness = <255>;
};
};
+ led-controller-2 {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_alarmled_pins>;
+
+ led-2 {
+ label = "alarm:red";
+ gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ label = "alarm:yellow";
+ gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-4 {
+ label = "alarm:blue";
+ gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-5 {
+ label = "alarm:silenced";
+ gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
- spidev0: spi@0 {
- compatible = "ge,achc";
- reg = <0>;
- spi-max-frequency = <1000000>;
- };
-
- spidev1: spi@1 {
- compatible = "ge,achc";
- reg = <1>;
- spi-max-frequency = <1000000>;
+ spidev0: spi@1 {
+ compatible = "ge,achc", "nxp,kinetis-k20";
+ reg = <1>, <0>;
+ vdd-supply = <®_3v3>;
+ vdda-supply = <®_3v3>;
+ clocks = <&achc_24M>;
+ reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
gpioxra0: gpio@2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
bus-width = <8>;
- non-removable;
status = "okay";
};
reg = <1>;
rtc@30 {
- compatible = "sii,s35392a-rtc";
+ compatible = "sii,s35390a";
reg = <0x30>;
};
touchscreen@4b {
compatible = "atmel,maxtouch";
- reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>;
reg = <0x4b>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ fsl,dma-info = <24 20>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
+ fsl,dma-info = <4096 4>;
status = "okay";
};
MX53_PAD_NANDF_CS3__GPIO6_16 0x0
/* POWER_AND_BOOT_STATUS_INDICATOR */
MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4
- /* ACTIVATE_ALARM_LIGHT_RED */
- MX53_PAD_PATA_DIOR__GPIO7_3 0x0
- /* ACTIVATE_ALARM_LIGHT_YELLOW */
- MX53_PAD_PATA_DA_1__GPIO7_7 0x0
- /* ACTIVATE_ALARM_LIGHT_CYAN */
- MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* RUNNING_ON_BATTERY_INDICATOR_GREEN */
MX53_PAD_GPIO_16__GPIO7_11 0x0
/* BATTERY_STATUS_INDICATOR_AMBER */
MX53_PAD_GPIO_17__GPIO7_12 0x0
- /* AUDIO_ALARMS_SILENCED_INDICATOR */
- MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180
>;
};
-};
-#include "imx53-ppd-uboot.dtsi"
+ pinctrl_alarmled_pins: qmx6alarmledgrp {
+ fsl,pins = <
+ /* ACTIVATE_ALARM_LIGHT_RED */
+ MX53_PAD_PATA_DIOR__GPIO7_3 0x0
+ /* ACTIVATE_ALARM_LIGHT_YELLOW */
+ MX53_PAD_PATA_DA_1__GPIO7_7 0x0
+ /* ACTIVATE_ALARM_LIGHT_CYAN */
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x0
+ /* AUDIO_ALARMS_SILENCED_INDICATOR */
+ MX53_PAD_GPIO_18__GPIO7_13 0x0
+ >;
+ };
+};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
- broken-cd;
status = "okay";
};
clocks {
ckil {
- compatible = "fsl,imx-ckil", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
- compatible = "fsl,imx-ckih1", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
- compatible = "fsl,imx-ckih2", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
- compatible = "fsl,imx-osc", "fixed-clock";
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
status = "okay";
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
clock-names = "core_clk", "mem_iface_clk";
};
- bus@50000000 { /* AIPS1 */
+ aips1: bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x10000000>;
ranges;
- spba@50000000 {
+ spba-bus@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
- esdhc1: esdhc@50004000 {
+ esdhc1: mmc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
status = "disabled";
};
- esdhc2: esdhc@50008000 {
+ esdhc2: mmc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
status = "disabled";
};
- esdhc3: esdhc@50020000 {
+ esdhc3: mmc@50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
status = "disabled";
};
- esdhc4: esdhc@50024000 {
+ esdhc4: mmc@50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
status = "disabled";
};
- wdog1: wdog@53f98000 {
+ wdog1: watchdog@53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
- wdog2: wdog@53f9c000 {
+ wdog2: watchdog@53f9c000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
};
pwm1: pwm@53fb4000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
};
pwm2: pwm@53fb8000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
status = "disabled";
};
- src: src@53fd0000 {
+ src: reset-controller@53fd0000 {
compatible = "fsl,imx53-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
+ interrupts = <75>;
#reset-cells = <1>;
};
};
};
- bus@60000000 { /* AIPS2 */
+ aips2: bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x63f00000 0x60>;
};
- iim: iim@63f98000 {
- compatible = "fsl,imx53-iim", "fsl,imx27-iim";
+ iim: efuse@63f98000 {
+ compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright 2013-2019 Boundary Devices, Inc.
-// Copyright 2012 Freescale Semiconductor, Inc.
-// Copyright 2011 Linaro Ltd.
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ */
/dts-v1/;
#include "imx6q.dtsi"
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Copyright 2013-2019 Boundary Devices, Inc.
-// Copyright 2012 Freescale Semiconductor, Inc.
-// Copyright 2011 Linaro Ltd.
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ */
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
};
&pcie {
- status = "disabled";
+ reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
};
&vgen3_reg {
};
};
+&vgen3_reg {
+ regulator-always-on;
+};
+
&pcie {
- status = "disabled";
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
};
};
&fec {
- /delete-property/interrupts-extended;
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
};
&pcie {
- compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6qp-pcie";
};
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+//Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
- memory {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
- backlight {
+ backlight_display: backlight_display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 0 0>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 2 0>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
- reg_aud3v: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "wm8962-supply-3v15";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
- regulator-boot-on;
- };
+ reg_aud3v: regulator-aud3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-boot-on;
+ };
- reg_aud4v: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "wm8962-supply-4v2";
- regulator-min-microvolt = <4325000>;
- regulator-max-microvolt = <4325000>;
- regulator-boot-on;
- };
+ reg_aud4v: regulator-aud4v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
- reg_lcd_3v3: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "lcd-3v3";
- gpio = <&gpio4 3 0>;
- enable-active-high;
- };
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
+ regulator-name = "lcd-3v3";
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lcd_5v: regulator-lcd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
+ hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ };
+
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&backlight_display>;
+ dvdd-supply = <®_lcd_3v3>;
+ avdd-supply = <®_lcd_5v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
};
};
};
&ecspi1 {
- cs-gpios = <&gpio4 11 0>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
- flash: m25p80@0 {
+ flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic: pfuze100@08 {
+ pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
swbst_reg: swbst {
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
>;
};
+ pinctrl_reg_lcd_3v3: reglcd3v3grp {
+ fsl,pins = <
+ MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
- lcd-supply = <®_lcd_3v3>;
- display = <&display0>;
status = "okay";
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <89>;
- hfront-porch = <164>;
- vback-porch = <23>;
- vfront-porch = <10>;
- hsync-len = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
+®_vdd1p1 {
+ vin-supply = <&sw2_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&sw2_reg>;
+};
+
&snvs_poweroff {
status = "okay";
};
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __DTS_IMX6SL_PINFUNC_H
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
- * Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
aliases {
ethernet0 = &fec;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ mmc3 = &usdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ usb2 = &usbh;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 996000 1275000
- 792000 1175000
- 396000 975000
- >;
- fsl,soc-operating-points = <
- /* ARM kHz SOC-PU uV */
- 996000 1225000
- 792000 1175000
- 396000 1175000
- >;
+ <996000 1275000>,
+ <792000 1175000>,
+ <396000 975000>;
+ fsl,soc-operating-points =
+ /* ARM kHz SOC-PU uV */
+ <996000 1225000>,
+ <792000 1175000>,
+ <396000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
- intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&gpc>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gpc>;
ranges;
- ocram: sram@00900000 {
+ ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
- L2: l2-cache@00a02000 {
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
arm,data-latency = <4 2 3>;
};
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- aips1: bus@02000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- spba: spba-bus@02000000 {
+ spba: spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
- spdif: spdif@02004000 {
+ spdif: spdif@2004000 {
compatible = "fsl,imx6sl-spdif",
"fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
status = "disabled";
};
- ecspi1: ecspi@02008000 {
+ ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi2: ecspi@0200c000 {
+ ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi3: ecspi@02010000 {
+ ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi4: ecspi@02014000 {
+ ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- uart5: serial@02018000 {
+ uart5: serial@2018000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
status = "disabled";
};
- uart1: serial@02020000 {
+ uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
status = "disabled";
};
- uart2: serial@02024000 {
+ uart2: serial@2024000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
status = "disabled";
};
- ssi1: ssi@02028000 {
+ ssi1: ssi@2028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
status = "disabled";
};
- ssi2: ssi@0202c000 {
+ ssi2: ssi@202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
status = "disabled";
};
- ssi3: ssi@02030000 {
+ ssi3: ssi@2030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
status = "disabled";
};
- uart3: serial@02034000 {
+ uart3: serial@2034000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
status = "disabled";
};
- uart4: serial@02038000 {
+ uart4: serial@2038000 {
compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
};
};
- pwm1: pwm@02080000 {
- #pwm-cells = <2>;
+ pwm1: pwm@2080000 {
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PWM1>,
+ clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM1>;
clock-names = "ipg", "per";
};
- pwm2: pwm@02084000 {
- #pwm-cells = <2>;
+ pwm2: pwm@2084000 {
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PWM2>,
+ clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM2>;
clock-names = "ipg", "per";
};
- pwm3: pwm@02088000 {
- #pwm-cells = <2>;
+ pwm3: pwm@2088000 {
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PWM3>,
+ clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM3>;
clock-names = "ipg", "per";
};
- pwm4: pwm@0208c000 {
- #pwm-cells = <2>;
+ pwm4: pwm@208c000 {
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PWM4>,
+ clocks = <&clks IMX6SL_CLK_PERCLK>,
<&clks IMX6SL_CLK_PWM4>;
clock-names = "ipg", "per";
};
- gpt: gpt@02098000 {
+ gpt: timer@2098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ipg", "per";
};
- gpio1: gpio@0209c000 {
+ gpio1: gpio@209c000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
};
- gpio2: gpio@020a0000 {
+ gpio2: gpio@20a0000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
};
- gpio3: gpio@020a4000 {
+ gpio3: gpio@20a4000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
<&iomuxc 31 102 1>;
};
- gpio4: gpio@020a8000 {
+ gpio4: gpio@20a8000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
};
- gpio5: gpio@020ac000 {
+ gpio5: gpio@20ac000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
<&iomuxc 21 161 1>;
};
- kpp: kpp@020b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
- wdog1: wdog@020bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
};
- wdog2: wdog@020c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
- clks: ccm@020c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
#clock-cells = <1>;
};
- anatop: anatop@020c8000 {
+ anatop: anatop@20c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1375000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2850000>;
+ regulator-min-microvolt = <2250000>;
+ regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
- regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
- };
- tempmon: tempmon {
- compatible = "fsl,imx6q-tempmon";
- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
+ tempmon: tempmon {
+ compatible = "fsl,imx6q-tempmon";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gpc>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
+ };
};
- usbphy1: usbphy@020c9000 {
+ usbphy1: usbphy@20c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
fsl,anatop = <&anatop>;
};
- usbphy2: usbphy@020ca000 {
+ usbphy2: usbphy@20ca000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
fsl,anatop = <&anatop>;
};
- snvs: snvs@020cc000 {
+ snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
};
- epit1: epit@020d0000 {
+ epit1: epit@20d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
};
- epit2: epit@020d4000 {
+ epit2: epit@20d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@020d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
#reset-cells = <1>;
};
- gpc: gpc@020dc000 {
+ gpc: gpc@20dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
- pu-supply = <®_pu>;
- clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
- <&clks IMX6SL_CLK_GPU2D_PODF>;
- #power-domain-cells = <1>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
+ clock-names = "ipg";
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_pu: power-domain@1 {
+ reg = <1>;
+ #power-domain-cells = <0>;
+ power-supply = <®_pu>;
+ clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+ <&clks IMX6SL_CLK_GPU2D_PODF>;
+ };
+
+ pd_disp: power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
+ <&clks IMX6SL_CLK_LCDIF_PIX>,
+ <&clks IMX6SL_CLK_EPDC_AXI>,
+ <&clks IMX6SL_CLK_EPDC_PIX>,
+ <&clks IMX6SL_CLK_PXP_AXI>;
+ };
+ };
};
- gpr: iomuxc-gpr@020e0000 {
+ gpr: iomuxc-gpr@20e0000 {
compatible = "fsl,imx6sl-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
- iomuxc: iomuxc@020e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
};
- csi: csi@020e4000 {
+ csi: csi@20e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
};
- spdc: spdc@020e8000 {
+ spdc: spdc@20e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};
- sdma: sdma@020ec000 {
+ sdma: sdma@20ec000 {
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SDMA>,
- <&clks IMX6SL_CLK_SDMA>;
+ <&clks IMX6SL_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
/* imx6sl reuses imx6q sdma firmware */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
- pxp: pxp@020f0000 {
+ pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
- epdc: epdc@020f4000 {
+ epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
- lcdif: lcdif@020f8000 {
+ lcdif: lcdif@20f8000 {
compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
+ power-domains = <&pd_disp>;
};
- dcp: dcp@020fc000 {
+ dcp: crypto@20fc000 {
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
};
};
- aips2: bus@02100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- usbotg1: usb@02184000 {
+ usbotg1: usb@2184000 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usbotg2: usb@02184200 {
+ usbotg2: usb@2184200 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usbh: usb@02184400 {
+ usbh: usb@2184400 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphynop1>;
+ phy_type = "hsic";
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
ahb-burst-config = <0x0>;
status = "disabled";
};
- usbmisc: usbmisc@02184800 {
+ usbmisc: usbmisc@2184800 {
#index-cells = <1>;
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
};
- fec: ethernet@02188000 {
+ fec: ethernet@2188000 {
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc1: usdhc@02190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc2: usdhc@02194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc3: usdhc@02198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc4: usdhc@0219c000 {
+ usdhc4: mmc@219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- i2c1: i2c@021a0000 {
+ i2c1: i2c@21a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- i2c2: i2c@021a4000 {
+ i2c2: i2c@21a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- i2c3: i2c@021a8000 {
+ i2c3: i2c@21a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- mmdc: mmdc@021b0000 {
+ memory-controller@21b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
+ clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
};
- rngb: rngb@021b4000 {
+ rngb: rngb@21b4000 {
+ compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_DUMMY>;
};
- weim: weim@021b8000 {
+ weim: weim@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
status = "disabled";
};
- ocotp: ocotp@021bc000 {
+ ocotp: efuse@21bc000 {
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
- audmux: audmux@021d8000 {
+ audmux: audmux@21d8000 {
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
};
+
+ gpu_2d: gpu@2200000 {
+ compatible = "vivante,gc";
+ reg = <0x02200000 0x4000>;
+ interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_GPU2D_OVG>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_pu>;
+ };
+
+ gpu_vg: gpu@2204000 {
+ compatible = "vivante,gc";
+ reg = <0x02204000 0x4000>;
+ interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+ <&clks IMX6SL_CLK_GPU2D_OVG>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_pu>;
+ };
};
};
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/dts-v1/;
model = "Freescale i.MX6SLL EVK Board";
compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
- memory {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x80000000>;
};
- backlight {
+ backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
status = "okay";
};
- battery: max8903@0 {
- compatible = "fsl,max8903-charger";
+ leds {
+ compatible = "gpio-leds";
pinctrl-names = "default";
- dok_input = <&gpio4 13 1>;
- uok_input = <&gpio4 13 1>;
- chg_input = <&gpio4 15 1>;
- flt_input = <&gpio4 14 1>;
- fsl,dcm_always_high;
- fsl,dc_valid;
- fsl,adc_disable;
- status = "okay";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user {
+ label = "debug";
+ gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
};
- pxp_v4l2_out {
- compatible = "fsl,imx6sl-pxp-v4l2";
- status = "okay";
+ reg_usb_otg1_vbus: regulator-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ reg_usb_otg2_vbus: regulator-otg2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_aud3v: regulator-aud3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-boot-on;
+ };
- reg_usb_otg2_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_aud4v: regulator-aud4v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
- reg_aud3v: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "wm8962-supply-3v15";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
- regulator-boot-on;
- };
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
+ regulator-name = "lcd-3v3";
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_aud4v: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "wm8962-supply-4v2";
- regulator-min-microvolt = <4325000>;
- regulator-max-microvolt = <4325000>;
- regulator-boot-on;
- };
+ reg_lcd_5v: regulator-lcd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
- reg_lcd: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "lcd-pwr";
- gpio = <&gpio4 8 0>;
- enable-active-high;
- };
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_sd1_vmmc: sd1_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "SD1_SPWR";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_sd3_vmmc: regulator-sd3-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_sd3_vmmc>;
+ regulator-name = "SD3_WIFI";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_sd2_vmmc: sd2_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "eMMC-VCCQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- };
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&backlight_display>;
+ dvdd-supply = <®_lcd_3v3>;
+ avdd-supply = <®_lcd_5v>;
- reg_sd3_vmmc: sd3_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "SD3_WIFI";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
};
-
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
- cpu-dai = <&ssi2>;
- audio-codec = <&codec>;
+ audio-cpu = <&ssi2>;
+ audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
- codec-master;
- hp-det-gpios = <&gpio4 24 1>;
+ hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
};
};
status = "okay";
};
-&clks {
- assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
- assigned-clock-rates = <393216000>;
-};
-
&cpu0 {
arm-supply = <&sw1a_reg>;
soc-supply = <&sw1c_reg>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic: pfuze100@08 {
+ pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
swbst_reg: swbst {
};
};
};
-
- max17135: max17135@48 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_max17135>;
- compatible = "maxim,max17135";
- reg = <0x48>;
- status = "okay";
-
- vneg_pwrup = <1>;
- gvee_pwrup = <2>;
- vpos_pwrup = <10>;
- gvdd_pwrup = <12>;
- gvdd_pwrdn = <1>;
- vpos_pwrdn = <2>;
- gvee_pwrdn = <8>;
- vneg_pwrdn = <10>;
- gpio_pmic_pwrgood = <&gpio2 13 0>;
- gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
- gpio_pmic_wakeup = <&gpio2 14 0>;
- gpio_pmic_v3p3 = <&gpio2 7 0>;
- gpio_pmic_intr = <&gpio2 12 0>;
-
- regulators {
- DISPLAY_reg: DISPLAY {
- regulator-name = "DISPLAY";
- };
-
- GVDD_reg: GVDD {
- /* 20v */
- regulator-name = "GVDD";
- };
-
- GVEE_reg: GVEE {
- /* -22v */
- regulator-name = "GVEE";
- };
-
- HVINN_reg: HVINN {
- /* -22v */
- regulator-name = "HVINN";
- };
-
- HVINP_reg: HVINP {
- /* 20v */
- regulator-name = "HVINP";
- };
-
- VCOM_reg: VCOM {
- regulator-name = "VCOM";
- /* 2's-compliment, -4325000 */
- regulator-min-microvolt = <0xffbe0178>;
- /* 2's-compliment, -500000 */
- regulator-max-microvolt = <0xfff85ee0>;
- };
-
- VNEG_reg: VNEG {
- /* -15v */
- regulator-name = "VNEG";
- };
-
- VPOS_reg: VPOS {
- /* 15v */
- regulator-name = "VPOS";
- };
-
- V3P3_reg: V3P3 {
- regulator-name = "V3P3";
- };
- };
- };
};
&i2c3 {
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
- codec: wm8962@1a {
+ wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <®_aud4v>;
SPKVDD2-supply = <®_aud4v>;
- amic-mono;
};
};
-&gpc {
- fsl,ldo-bypass = <1>;
-};
-
-&iomuxc {
+&lcdif {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- imx6sll-evk {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
- MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
- MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
- /*
- * Must set the LVE of pad SD2_RESET, otherwise current
- * leakage through eMMC chip will pull high the VCCQ to
- * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
- */
- MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
- MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
- MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
- MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
- MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
- MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
- /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
- MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
- MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
- MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
- >;
- };
-
- pinctrl_audmux3: audmux3grp {
- fsl,pins = <
- MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
- MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
- MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
- MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
- MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
- >;
- };
-
- pinctrl_csi1: csi1grp {
- fsl,pins = <
- MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
- MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
- MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
- MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
- MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
- MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
- MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
- MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
- MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
- MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
- MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
- MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
- MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
- MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
- >;
- };
-
- pinctrl_epdc0: epdcgrp0 {
- fsl,pins = <
- MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
- MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
- MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
- MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
- MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
- MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
- MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
- MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
- MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
- MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
- MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
- MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
- MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
- MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
- MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
- MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
- MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
- MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
- MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
- MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
- MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
- MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
- MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
- MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
- MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
- >;
- };
-
- pinctrl_lcdif_dat: lcdifdatgrp {
- fsl,pins = <
- MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
- MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
- MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
- MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
- MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
- MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
- MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
- MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
- MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
- MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
- MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
- MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
- MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
- MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
- MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
- MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
- MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
- MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
- MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
- MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
- MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
- MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
- MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
- MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
- >;
- };
-
- pinctrl_lcdif_ctrl: lcdifctrlgrp {
- fsl,pins = <
- MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
- MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
- MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
- MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
- MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
- MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
- >;
- };
-
- pinctrl_max17135: max17135grp-1 {
- fsl,pins = <
- MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
- MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
- MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
- MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
- MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
- >;
- };
-
- pinctrl_spdif: spdifgrp {
- fsl,pins = <
- MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
- MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
- MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
- MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
- MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
- MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart5dte: uart5dtegrp {
- fsl,pins = <
- MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
- MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
- MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
- MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
- fsl,pins = <
- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
- fsl,pins = <
- MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
- MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
- MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
- MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
- MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
- MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
- MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
- MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
- MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
- MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
- fsl,pins = <
- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
- MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
- MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
- MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
- MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
- MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
- fsl,pins = <
- MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
- MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
- MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
- MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
- MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
- MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
- MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
- MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
- MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
- MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059
- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
- fsl,pins = <
- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9
- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
- fsl,pins = <
- MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
- MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
- MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
- MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
- MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
- MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
- >;
- };
-
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
- MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
- MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
- >;
- };
+ pinctrl-0 = <&pinctrl_lcd>;
+ status = "okay";
- pinctrl_pwm1: pmw1grp {
- fsl,pins = <
- MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
- >;
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
-&lcdif {
+&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif_dat
- &pinctrl_lcdif_ctrl>;
- lcd-supply = <®_lcd>;
- display = <&display>;
+ pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
+};
- display: display {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <89>;
- hfront-porch = <164>;
- vback-porch = <23>;
- vfront-porch = <10>;
- hsync-len = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
- };
+&snvs_poweroff {
+ status = "okay";
};
-&pxp {
+&snvs_pwrkey {
status = "okay";
};
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
+&ssi2 {
status = "okay";
};
status = "okay";
};
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- fsl,uart-has-rtscts;
- /* for DTE mode, add below change */
- /* fsl,dte-mode; */
- /* pinctrl-0 = <&pinctrl_uart5dte>; */
- status = "disabled";
-};
-
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
- enable-sdio-wakeup;
+ wakeup-source;
vmmc-supply = <®_sd1_vmmc>;
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- vqmmc-supply = <®_sd2_vmmc>;
- bus-width = <8>;
- no-removable;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- keep-power-in-suspend;
- enable-sdio-wakeup;
- vmmc-supply = <®_sd3_vmmc>;
- status = "okay";
-};
-
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
pinctrl-names = "default";
status = "okay";
};
-&epdc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_epdc0>;
- V3P3-supply = <&V3P3_reg>;
- VCOM-supply = <&VCOM_reg>;
- DISPLAY-supply = <&DISPLAY_reg>;
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_sd3_vmmc>;
status = "okay";
};
-&ssi2 {
- status = "okay";
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_audmux3: audmux3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
+ MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
+ MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
+ MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
+ MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+ >;
+ };
+
+ pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg1_vbus: vbus1grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg2_vbus: vbus2grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+ >;
+ };
+
+ pinctrl_reg_lcd_3v3: reglcd3v3grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
+ >;
+ };
+
+ pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061
+ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1
+ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9
+ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
+ MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
+ >;
+ };
+
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
+ MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
+ MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
+ MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
+ MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
+ MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
+ MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
+ MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
+ MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
+ MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
+ MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
+ MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+ MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
+ MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059
+ >;
+ };
+
+ pinctrl_pwm1: pmw1grp {
+ fsl,pins = <
+ MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_wdog1: wdog1grp {
+ fsl,pins = <
+ MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0
+ >;
+ };
};
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP.
*
*/
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <dt-bindings/clock/imx6sll-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sll-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
spi1 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 996000 1225000
- 792000 1175000
- 396000 1075000
- 198000 975000
- >;
- fsl,soc-operating-points = <
+ <996000 1275000>,
+ <792000 1175000>,
+ <396000 1075000>,
+ <198000 975000>;
+ fsl,soc-operating-points =
/* ARM kHz SOC-PU uV */
- 996000 1225000
- 792000 1175000
- 396000 1175000
- 198000 1175000
- >;
+ <996000 1175000>,
+ <792000 1175000>,
+ <396000 1175000>,
+ <198000 1175000>;
clock-latency = <61036>; /* two CLK32 periods */
- fsl,low-power-run;
+ #cooling-cells = <2>;
clocks = <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL2_PFD2>,
<&clks IMX6SLL_CLK_STEP>,
<&clks IMX6SLL_CLK_PLL1_SW>,
- <&clks IMX6SLL_CLK_PLL1_SYS>,
- <&clks IMX6SLL_CLK_PLL1>,
- <&clks IMX6SLL_PLL1_BYPASS>,
- <&clks IMX6SLL_PLL1_BYPASS_SRC>;
+ <&clks IMX6SLL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
- "pll1_bypass_src";
+ "pll1_sw", "pll1_sys";
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
- intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
+ ckil: clock-ckil {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
};
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ckil: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "ckil";
- };
-
- osc: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "osc";
- };
+ osc: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
- ipp_di0: clock@2 {
- compatible = "fixed-clock";
- reg = <2>;
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "ipp_di0";
- };
+ ipp_di0: clock-ipp-di0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
- ipp_di1: clock@3 {
- compatible = "fixed-clock";
- reg = <3>;
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "ipp_di1";
- };
+ ipp_di1: clock-ipp-di1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
};
soc {
interrupt-parent = <&gpc>;
ranges;
- busfreq {
- compatible = "fsl,imx_busfreq";
- clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
- <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
- <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
- <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
- <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
- <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
- <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
- <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
- <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
- <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
- <&clks IMX6SLL_CLK_PLL1>;
- clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
- "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
- "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
- "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
- fsl,max_ddr_freq = <400000000>;
- };
-
- ocrams: sram@00900000 {
- compatible = "fsl,lpm-sram";
- reg = <0x00900000 0x4000>;
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
};
- ocrams_ddr: sram@00904000 {
- compatible = "fsl,ddr-lpm-sram";
- reg = <0x00904000 0x1000>;
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
};
- ocram: sram@00905000 {
- compatible = "mmio-sram";
- reg = <0x00905000 0x1B000>;
- };
-
- L2: l2-cache@00a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
arm,data-latency = <4 2 3>;
};
- aips1: bus@02000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- spba: spba-bus@02000000 {
+ spba: spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
- spdif: spdif@02004000 {
+ spdif: spdif@2004000 {
compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ecspi1: ecspi@02008000 {
+ ecspi1: spi@2008000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ecspi2: ecspi@0200c000 {
+ ecspi2: spi@200c000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ecspi3: ecspi@02010000 {
+ ecspi3: spi@2010000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ecspi4: ecspi@02014000 {
+ ecspi4: spi@2014000 {
compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart4: serial@02018000 {
- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ uart4: serial@2018000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+ "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
- interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
status = "disabled";
};
- uart1: serial@02020000 {
- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ uart1: serial@2020000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+ "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
status = "disabled";
};
- uart2: serial@02024000 {
- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ uart2: serial@2024000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+ "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
status = "disabled";
};
- ssi1: ssi@02028000 {
- compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ ssi1: ssi@2028000 {
+ compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
status = "disabled";
};
- ssi2: ssi2@0202c000 {
- compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ ssi2: ssi@202c000 {
+ compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
status = "disabled";
};
- ssi3: ssi@02030000 {
- compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ ssi3: ssi@2030000 {
+ compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
status = "disabled";
};
- uart3: serial@02034000 {
- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ uart3: serial@2034000 {
+ compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
+ "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
};
};
- pwm1: pwm@02080000 {
+ pwm1: pwm@2080000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM1>,
<&clks IMX6SLL_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
- pwm2: pwm@02084000 {
+ pwm2: pwm@2084000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM2>,
<&clks IMX6SLL_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
- pwm3: pwm@02088000 {
+ pwm3: pwm@2088000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM3>,
<&clks IMX6SLL_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
- pwm4: pwm@0208c000 {
+ pwm4: pwm@208c000 {
compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_PWM4>,
<&clks IMX6SLL_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
- gpt1: gpt@02098000 {
- compatible = "fsl,imx6sll-gpt";
+ gpt1: timer@2098000 {
+ compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
clock-names = "ipg", "per";
};
- gpio1: gpio@0209c000 {
+ gpio1: gpio@209c000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
};
- gpio2: gpio@020a0000 {
+ gpio2: gpio@20a0000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 50 32>;
};
- gpio3: gpio@020a4000 {
+ gpio3: gpio@20a4000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
+ <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
+ <&iomuxc 21 6 11>;
};
- gpio4: gpio@020a8000 {
+ gpio4: gpio@20a8000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- };
-
- gpio5: gpio@020ac000 {
+ gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
+ <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
+ <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
+ <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
+ <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
+ <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
+ <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
+ <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
+ <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
+ };
+
+ gpio5: gpio@20ac000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- };
-
- gpio6: gpio@020b0000 {
+ gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
+ <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
+ <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
+ <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
+ <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
+ <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
+ <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
+ <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
+ <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
+ <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
+ <&iomuxc 21 137 1>;
+ };
+
+ gpio6: gpio@20b0000 {
compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
- kpp: kpp@020b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- wdog1: wdog@020bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_WDOG1>;
};
- wdog2: wdog@020c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- clks: ccm@020c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+
+ assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
+ assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
};
- anatop: anatop@020c8000 {
+ anatop: anatop@20c8000 {
compatible = "fsl,imx6sll-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x4000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_3p0: regulator-3p0@120 {
+ reg_3p0: regulator-3p0@20c8120 {
compatible = "fsl,anatop-regulator";
+ reg = <0x20c8120>;
regulator-name = "vdd3p0";
regulator-min-microvolt = <2625000>;
regulator-max-microvolt = <3400000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
- };
- tempmon: tempmon {
- compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
- status = "disabled";
+ tempmon: temperature-sensor {
+ compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gpc>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+ };
};
- usbphy1: usbphy@020c9000 {
+ usbphy1: usb-phy@20c9000 {
compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
"fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
fsl,anatop = <&anatop>;
};
- usbphy2: usbphy@020ca000 {
+ usbphy2: usb-phy@20ca000 {
compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
"fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
fsl,anatop = <&anatop>;
};
- snvs: snvs@020cc000 {
+ snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs_poweroff: snvs-poweroff {
regmap = <&snvs>;
offset = <0x38>;
mask = <0x61>;
+ status = "disabled";
};
snvs_pwrkey: snvs-powerkey {
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
- wakeup;
+ wakeup-source;
+ status = "disabled";
};
};
- epit1: epit@020d0000 {
- reg = <0x020d0000 0x4000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- epit2: epit@020d4000 {
- reg = <0x020d4000 0x4000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- src: src@020d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6sll-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
#reset-cells = <1>;
};
- gpc: gpc@020dc000 {
+ gpc: interrupt-controller@20dc000 {
compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
- fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
};
- iomuxc: iomuxc@020e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sll-iomuxc";
reg = <0x020e0000 0x4000>;
};
- gpr: iomuxc-gpr@020e4000 {
+ gpr: iomuxc-gpr@20e4000 {
compatible = "fsl,imx6sll-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
- csi: csi@020e8000 {
+ csi: csi@20e8000 {
compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
reg = <0x020e8000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdma: sdma@020ec000 {
- compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+ sdma: dma-controller@20ec000 {
+ compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SLL_CLK_SDMA>,
+ clocks = <&clks IMX6SLL_CLK_IPG>,
<&clks IMX6SLL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
- pxp: pxp@020f0000 {
- compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
- reg = <0x020f0000 0x4000>;
+ pxp: pxp@20f0000 {
+ compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
+ reg = <0x20f0000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SLL_CLK_DUMMY>,
- <&clks IMX6SLL_CLK_PXP>;
- clock-names = "pxp_ipg", "pxp_axi";
- status = "disabled";
- };
-
- epdc: epdc@020f4000 {
- compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
- reg = <0x020f4000 0x4000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
- clock-names = "epdc_axi", "epdc_pix";
- status = "disabled";
+ clocks = <&clks IMX6SLL_CLK_PXP>;
+ clock-names = "axi";
};
- lcdif: lcdif@020f8000 {
+ lcdif: lcd-controller@20f8000 {
compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- dcp: dcp@020fc000 {
- compatible = "fsl,imx6sl-dcp";
+ dcp: crypto@20fc000 {
+ compatible = "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
};
};
- aips2: bus@02100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- usbotg1: usb@02184000 {
+ usbotg1: usb@2184000 {
compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
reg = <0x02184000 0x200>;
status = "disabled";
};
- usbotg2: usb@02184200 {
+ usbotg2: usb@2184200 {
compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
reg = <0x02184200 0x200>;
status = "disabled";
};
- usbmisc: usbmisc@02184800 {
+ usbmisc: usbmisc@2184800 {
#index-cells = <1>;
compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
};
- usdhc1: usdhc@02190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc2: usdhc@02194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc3: usdhc@02198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- i2c1: i2c@021a0000 {
+ i2c1: i2c@21a0000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
+ compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_I2C1>;
status = "disabled";
};
- i2c2: i2c@021a4000 {
+ i2c2: i2c@21a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- i2c3: i2c@021a8000 {
+ i2c3: i2c@21a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- romcp@021ac000 {
- compatible = "fsl,imx6sll-romcp", "syscon";
- reg = <0x021ac000 0x4000>;
- };
-
- mmdc: mmdc@021b0000 {
+ mmdc: memory-controller@21b0000 {
compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
+ clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
- rngb: rngb@021b4000 {
- compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
+ rngb: rng@21b4000 {
+ compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
reg = <0x021b4000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SLL_CLK_DUMMY>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>;
};
- ocotp: ocotp-ctrl@021bc000 {
+ ocotp: efuse@21bc000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,imx6sll-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SLL_CLK_OCOTP>;
- };
- csu: csu@021c0000 {
- compatible = "fsl,imx6sll-csu";
- reg = <0x021c0000 0x4000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
- snvs_gpr: snvs-gpr@0x021c4000 {
- compatible = "fsl, imx6sll-snvs-gpr";
- reg = <0x021c4000 0x10000>;
- };
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
- iomuxc_snvs: iomuxc-snvs@021c8000 {
- compatible = "fsl,imx6sll-iomuxc-snvs";
- reg = <0x021c80000 0x10000>;
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
- audmux: audmux@021d8000 {
+ audmux: audmux@21d8000 {
compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
- uart5: serial@021f4000 {
- compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ uart5: serial@21f4000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
+ "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
- interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
/dts-v1/;
model = "Freescale i.MX6 SoloX Sabre Auto Board";
compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x80000000>;
};
- regulators {
- compatible = "simple-bus";
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user {
+ label = "debug";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc_sd3: regulator-vcc-sd3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_wake: regulator-can-wake {
+ compatible = "regulator-fixed";
+ regulator-name = "can-wake";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ regulator-name = "can-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_wake>;
+ };
+
+ reg_can_stby: regulator-can-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can_en>;
+ };
+
+ reg_cs42888: cs42888_supply {
+ compatible = "regulator-fixed";
+ regulator-name = "cs42888_supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound-cs42888 {
+ compatible = "fsl,imx6-sabreauto-cs42888",
+ "fsl,imx-audio-cs42888";
+ model = "imx-cs42888";
+ audio-cpu = <&esai>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&cs42888>;
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "Line In Jack",
+ "AIN1R", "Line In Jack",
+ "AIN2L", "Line In Jack",
+ "AIN2R", "Line In Jack";
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ };
+};
+
+&anaclk2 {
+ clock-frequency = <24576000>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
+ <&clks IMX6SX_PLL4_BYPASS>,
+ <&clks IMX6SX_CLK_PLL4_POST_DIV>;
+ assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
+ <&clks IMX6SX_PLL4_BYPASS_SRC>;
+ assigned-clock-rates = <0>, <0>, <24576000>;
+};
+
+&esai {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esai>;
+ assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
+ <&clks IMX6SX_CLK_ESAI_EXTAL>;
+ assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <24576000>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
- vcc_sd3: regulator@0 {
- compatible = "regulator-fixed";
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_vcc_sd3>;
- regulator-name = "VCC_SD3";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
};
};
};
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
+&iomuxc {
+ pinctrl_egalax_int: egalax-intgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
+ >;
+ };
+
+ pinctrl_esai: esaigrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
+ MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
+ MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
+ MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
+ MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
+ MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
+ MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
+ MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
+ MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
+ MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
+ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
+ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
+ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
+ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
+ >;
+ };
+
+ pinctrl_vcc_sd3: vccsd3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
+
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_1>;
+ pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ cs42888: cs42888@48 {
+ compatible = "cirrus,cs42888";
+ reg = <0x48>;
+ clocks = <&anaclk2 0>;
+ clock-names = "mclk";
+ VA-supply = <®_cs42888>;
+ VD-supply = <®_cs42888>;
+ VLS-supply = <®_cs42888>;
+ VLC-supply = <®_cs42888>;
+ };
+
+ touchscreen@4 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_egalax_int>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&i2c3 {
- clock-frequency = <100000>;
+ clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_2>;
+ pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
max7310_a: gpio@30 {
};
};
-&qspi1 {
+&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi1_1>;
+ pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
+ assigned-clock-rates = <24576000>;
status = "okay";
- ddrsmp=<2>;
-
- flash0: n25q256a@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a";
- spi-max-frequency = <29000000>;
- reg = <0>;
- };
-
- flash1: n25q256a@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a";
- spi-max-frequency = <29000000>;
- reg = <1>;
- };
};
-&iomuxc {
- imx6x-sabreauto {
- pinctrl_i2c2_1: i2c2grp-1 {
- fsl,pins = <
- MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
- MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3_2: i2c3grp-2 {
- fsl,pins = <
- MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
- MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
- >;
- };
-
- pinctrl_qspi1_1: qspi1grp_1 {
- fsl,pins = <
- MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
- MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
- MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
- MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
- MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
- MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
- MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
- MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
- MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
- MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
- MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
- MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
- MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
- MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
- >;
- };
-
- pinctrl_usdhc4: usdhc4grp {
- fsl,pins = <
- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
- MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
- MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
- >;
- };
-
- pinctrl_vcc_sd3: vccsd3grp {
- fsl,pins = <
- MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
- >;
- };
- };
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
};
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
- flash0: n25q256a@0 {
+ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
- spi-tx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
reg = <0>;
};
- flash1: n25q256a@2 {
+ flash1: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
- spi-tx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
reg = <2>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
+ hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
panel {
};
};
};
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif",
+ "fsl,imx6sx-sdb-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-out;
+ };
+
};
&audmux {
phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
status = "okay";
mdio {
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <ðphy2>;
+ fsl,magic-packet;
status = "okay";
};
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
status = "disabled";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&ssi2 {
status = "okay";
};
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
>;
};
+ pinctrl_mqs: mqsgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
+ MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
>;
};
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
- MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
- MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
- MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
- MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+ MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
+ MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
+ MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
+ MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
>;
};
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
/dts-v1/;
model = "Softing VIN|ING 2000";
compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
- aliases {
- mmc0 = &usdhc4;
- mmc1 = &usdhc2;
- };
-
chosen {
stdout-path = &uart1;
};
regulator-max-microvolt = <3300000>;
};
- pwmleds {
+ led-controller {
compatible = "pwm-leds";
- red {
+ led-1 {
label = "red";
max-brightness = <255>;
pwms = <&pwm6 0 50000>;
};
- green {
+ led-2 {
label = "green";
max-brightness = <255>;
pwms = <&pwm2 0 50000>;
};
- blue {
+ led-3 {
label = "blue";
max-brightness = <255>;
pwms = <&pwm1 0 50000>;
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
status = "okay";
};
-®_pcie {
- regulator-always-on;
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
>;
};
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+ status = "okay";
+};
+
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm6 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
status = "okay";
};
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ hdmi-transmitter@70 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
+ interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>;
+
+ ports {
+ port {
+ hdmi: endpoint {
+ remote-endpoint = <&lcdc>;
+ };
+ };
+ };
+ };
+};
+
&i2c4 { /* Onboard Motion sensors */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "disabled";
};
+&lcdif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd>;
+ status = "okay";
+
+ port {
+ lcdc: endpoint {
+ remote-endpoint = <&hdmi>;
+ };
+ };
+};
+
&iomuxc {
pinctrl_bt_reg: btreggrp {
fsl,pins =
- <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
+ <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
};
pinctrl_enet1: enet1grp {
<MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins =
+ <MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1>,
+ <MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1>;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>,
<MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>;
};
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
+ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>,
pinctrl_otg1_reg: otg1grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
+ <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>;
};
-
pinctrl_otg2_reg: otg2grp {
fsl,pins =
- <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
+ <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
- <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
+ <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>,
+ <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins =
- <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
+ <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>;
};
pinctrl_usdhc2: usdhc2grp {
spi2 = &ecspi3;
spi3 = &ecspi4;
spi4 = &ecspi5;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ usb2 = &usbh;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
clock-output-names = "anaclk2";
};
- tempmon: tempmon {
- compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
- interrupt-parent = <&gpc>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ mqs: mqs {
+ compatible = "fsl,imx6sx-mqs";
+ gpr = <&gpr>;
+ status = "disabled";
};
pmu {
#phy-cells = <0>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
};
- L2: l2-cache@a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
- gpmi: gpmi-nand@1806000{
+ gpmi: nand-controller@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
};
esai: esai@2024000 {
+ compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal",
"fsys", "spba";
+ dmas = <&sdma 23 21 0>,
+ <&sdma 24 21 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
};
asrc: asrc@2034000 {
+ compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
- <&clks IMX6SX_CLK_ASRC_IPG>,
- <&clks IMX6SX_CLK_SPDIF>,
- <&clks IMX6SX_CLK_SPBA>;
- clock-names = "mem", "ipg", "asrck", "spba";
- dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
- <&sdma 19 20 1>, <&sdma 20 20 1>,
- <&sdma 21 20 1>, <&sdma 22 20 1>;
+ clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
+ <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
+ <&sdma 19 23 1>, <&sdma 20 23 1>,
+ <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
status = "okay";
};
};
clocks = <&clks IMX6SX_CLK_PWM1>,
<&clks IMX6SX_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm2: pwm@2084000 {
clocks = <&clks IMX6SX_CLK_PWM2>,
<&clks IMX6SX_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm3: pwm@2088000 {
clocks = <&clks IMX6SX_CLK_PWM3>,
<&clks IMX6SX_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm4: pwm@208c000 {
clocks = <&clks IMX6SX_CLK_PWM4>,
<&clks IMX6SX_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
flexcan1: can@2090000 {
clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
<&clks IMX6SX_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
- fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
+ fsl,stop-mode = <&gpr 0x10 1>;
status = "disabled";
};
clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
<&clks IMX6SX_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
- fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
+ fsl,stop-mode = <&gpr 0x10 2>;
status = "disabled";
};
- gpt: gpt@2098000 {
+ gpt: timer@2098000 {
compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
};
- kpp: kpp@20b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- wdog1: wdog@20bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_IPG>;
};
- wdog2: wdog@20c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- clks: ccm@20c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ };
};
usbphy1: usbphy@20c9000 {
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@20d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
};
};
- iomuxc: iomuxc@20e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sx-iomuxc";
reg = <0x020e0000 0x4000>;
};
reg = <0x02100000 0x100000>;
ranges;
- crypto: caam@2100000 {
+ crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
<&clks IMX6SX_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
status = "disabled";
};
- usdhc1: usdhc@2190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc2: usdhc@2194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc3: usdhc@2198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc4: usdhc@219c000 {
+ usdhc4: mmc@219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
status = "disabled";
};
- ocotp: ocotp@21bc000 {
+ ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
status = "disabled";
};
- wdog3: wdog@2288000 {
+ wdog3: watchdog@2288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x02288000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_PWM5>,
<&clks IMX6SX_CLK_PWM5>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm6: pwm@22a8000 {
clocks = <&clks IMX6SX_CLK_PWM6>,
<&clks IMX6SX_CLK_PWM6>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm7: pwm@22ac000 {
clocks = <&clks IMX6SX_CLK_PWM7>,
<&clks IMX6SX_CLK_PWM7>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm8: pwm@22b0000 {
clocks = <&clks IMX6SX_CLK_PWM8>,
<&clks IMX6SX_CLK_PWM8>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
pcie: pcie@8ffc000 {
- compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
+ compatible = "fsl,imx6sx-pcie";
reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
+ <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
display0 = &lcdif;
};
-&{/soc} {
+&soc {
u-boot,dm-pre-reloc;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include "imx6ul-kontron-bl.dts"
+
+/ {
+ model = "Kontron BL i.MX6UL 43 (N631X S 43)";
+ compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
+ "kontron,sl-imx6ul", "fsl,imx6ul";
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm7 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+};
+
+&i2c4 {
+ touchscreen@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cap_touch>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+ irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
+ /* Leave status disabled because of missing display panel node */
+};
+
+&pwm7 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_cap_touch: captouchgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
+ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
+ >;
+ };
+};
* Copyright (C) 2018 Kontron Electronics GmbH
*/
-#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
+#include "imx6ul-kontron-bl-common-u-boot.dtsi"
/dts-v1/;
-#include "imx6ul-kontron-n631x-som.dtsi"
-#include "imx6ul-kontron-n6x1x-s.dtsi"
+#include "imx6ul-kontron-sl.dtsi"
+#include "imx6ul-kontron-bl-common.dtsi"
/ {
- model = "Kontron N631X S";
- compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
- "fsl,imx6ul";
+ model = "Kontron BL i.MX6UL (N631X S)";
+ compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2018 Kontron Electronics GmbH
- * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "imx6ul-kontron-n6x1x-som.dtsi"
-
-/ {
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led1 {
- label = "debug-led1";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- label = "debug-led2";
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- label = "debug-led3";
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pwm-beeper {
- compatible = "pwm-beeper";
- pwms = <&pwm8 0 5000>;
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vref_adc: regulator-vref-adc {
- compatible = "regulator-fixed";
- regulator-name = "vref-adc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc1>;
- num-channels = <3>;
- vref-supply = <®_vref_adc>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- eeprom@0 {
- compatible = "anvo,anv32e61w", "atmel,at25";
- reg = <0>;
- spi-max-frequency = <20000000>;
- spi-cpha;
- spi-cpol;
- pagesize = <1>;
- size = <8192>;
- address-width = <16>;
- };
-};
-
-&fec1 {
- pinctrl-0 = <&pinctrl_enet1>;
- /delete-node/ mdio;
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
- phy-mode = "rmii";
- phy-handle = <ðphy2>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET2_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- rtc@32 {
- compatible = "epson,rx8900";
- reg = <0x32>;
- };
-};
-
-&pwm8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm8>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- linux,rs485-enabled-at-boot-time;
- rs485-rx-during-tx;
- rs485-rts-active-low;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- fsl,uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- dr_mode = "otg";
- srp-disable;
- hnp-disable;
- adp-disable;
- over-current-active-low;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- vbus-supply = <®_5v>;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <®_3v3>;
- voltage-ranges = <3300 3300>;
- bus-width = <4>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- non-removable;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <®_3v3>;
- voltage-ranges = <3300 3300>;
- bus-width = <4>;
- no-1-8-v;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
-
- pinctrl_adc1: adc1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
- MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
- MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
- >;
- };
-
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
- >;
- };
-
- pinctrl_enet2_mdio: enet2mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp{
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
- >;
- };
-
- pinctrl_gpio: gpiogrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
- MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
- >;
- };
-
- pinctrl_pwm8: pwm8grp {
- fsl,pins = <
- MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
- MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
- /*
- * mux unused RTS to make sure it doesn't cause
- * any interrupts when it is undefined
- */
- MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1: usbotg1 {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
- >;
- };
-};
chosen {
stdout-path = &uart4;
};
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ device_type = "memory";
+ };
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
};
&wdog1 {
*/
#include "imx6ul.dtsi"
-#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+#include "imx6ul-kontron-sl-common.dtsi"
/ {
- model = "Kontron N631X SOM";
- compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
+ model = "Kontron SL i.MX6UL (N631X SOM)";
+ compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
vref-supply = <®_adc1_vref_3v3>;
- /*
- * driver can not separate a specific channel so we request 4 channels
- * here - we need only the fourth channel
- */
- num-channels = <4>;
status = "disabled";
};
clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1025000
- 198000 950000
- >;
- fsl,soc-operating-points = <
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1025000>,
+ <198000 950000>;
+ fsl,soc-operating-points =
/* KHz uV */
- 696000 1275000
- 528000 1175000
- 396000 1175000
- 198000 1175000
- >;
+ <696000 1275000>,
+ <528000 1175000>,
+ <396000 1175000>,
+ <198000 1175000>;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
};
- soc {
+ soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
intc: interrupt-controller@a01000 {
};
kpp: keypad@20b8000 {
- compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+ compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_KPP>;
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
- num-channels = <2>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
};
csi: csi@21c4000 {
- compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
+ compatible = "fsl,imx6ul-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
};
lcdif: lcdif@21c8000 {
- compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+ compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
reg = <0x021c8000 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+ compatible = "fsl,imx6ul-qspi";
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
&adc1 {
- num-channels = <10>;
vref-supply = <®_module_3v3_avdd>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
atmel_mxt_ts: touchscreen@4a {
compatible = "atmel,maxtouch";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_atmel_conn>;
+ pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
reg = <0x4a>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
pinctrl_atmel_conn: atmelconngrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
};
&iomuxc_snvs {
+ pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
+ >;
+ };
+
pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
* Copyright (C) 2018 Kontron Electronics GmbH
*/
-#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"
+#include "imx6ul-kontron-bl-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-sl.dtsi"
+#include "imx6ul-kontron-bl-common.dtsi"
+
+/ {
+ model = "Kontron BL i.MX6ULL (N641X S)";
+ compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2017 exceet electronics GmbH
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6ull-kontron-n641x-som.dtsi"
-#include "imx6ul-kontron-n6x1x-s.dtsi"
-
-/ {
- model = "Kontron N641X S";
- compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
- "fsl,imx6ull";
-};
*/
#include "imx6ull.dtsi"
-#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+#include "imx6ul-kontron-sl-common.dtsi"
/ {
- model = "Kontron N641X SOM";
- compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
+ model = "Kontron SL i.MX6ULL (N641X SOM)";
+ compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
};
};
/ {
- soc {
+ soc: soc {
aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
/delete-property/ serial7;
/delete-property/ spi2;
/delete-property/ spi3;
- /delete-property/ spi4;
};
};
u-boot,dm-spl;
};
-&gpio0 {
+&gpio_ptc {
u-boot,dm-spl;
};
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2019 NXP
-// Author: Fabio Estevam <fabio.estevam@nxp.com>
/dts-v1/;
#include "imx7ulp.dtsi"
-#include "imx7ulp-com-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Embedded Artists i.MX7ULP COM";
stdout-path = &lpuart4;
};
- memory {
+ memory@60000000 {
device_type = "memory";
- reg = <0x60000000 0x8000000>;
+ reg = <0x60000000 0x4000000>;
};
};
status = "okay";
};
-&usbphy1 {
- fsl,tx-d-cal = <88>;
-};
-
&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
non-removable;
};
&iomuxc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_1>;
-
- pinctrl_hog_1: hoggrp-1 {
+ pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
- IMX7ULP_PAD_PTC1__PTC1 0x20000
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>;
};
- pinctrl_lpuart4: lpuart4grp {
+ pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};
-
- pinctrl_usbotg1_id: otg1idgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC13__USB0_ID 0x10003
- >;
- };
};
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
*/
/dts-v1/;
/ {
model = "NXP i.MX7ULP EVK";
- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
chosen {
- bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
stdout-path = &lpuart4;
};
- bcmdhd_wlan_0: bcmdhd_wlan@0 {
- compatible = "android,bcmdhd_wlan";
- wlreg_on-supply = <&wlreg_on>;
- bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
- bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
- };
-
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
backlight {
- compatible = "gpio-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
- default-on;
+ compatible = "pwm-backlight";
+ pwms = <&tpm4 1 50000 0>;
+ brightness-levels = <0 20 25 30 35 40 100>;
+ default-brightness-level = <6>;
status = "okay";
};
- mipi_dsi_reset: mipi-dsi-reset {
- compatible = "gpio-reset";
- reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- #reset-cells = <0>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- wlreg_on: fixedregulator@100 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-name = "wlreg_on";
- gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <100>;
- enable-active-high;
- };
-
- reg_usb_otg1_vbus: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_vbus>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vsd_3v3: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- };
-
- pf1550-rpmsg {
- compatible = "fsl,pf1550-rpmsg";
- sw1_reg: SW1 {
- regulator-name = "SW1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1387500>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw2_reg: SW2 {
- regulator-name = "SW2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1387500>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3_reg: SW3 {
- regulator-name = "SW3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: VREFDDR {
- regulator-name = "VREFDDR";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vldo1_reg: LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vldo2_reg: LDO2 {
- regulator-name = "LDO2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vldo3_reg: LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
-};
-
-&iomuxc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog_1>;
-
- imx7ulp-evk {
- pinctrl_hog_1: hoggrp-1 {
- fsl,pins = <
- IMX7ULP_PAD_PTC1__PTC1 0x20000
- >;
- };
-
- pinctrl_backlight: backlight_grp {
- fsl,pins = <
- IMX7ULP_PAD_PTF2__PTF2 0x20000
- >;
- };
-
- pinctrl_lpi2c5: lpi2c5grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
- IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
- >;
- };
-
- pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC19__PTC19 0x20003
- >;
- };
-
- pinctrl_lpuart4: lpuart4grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
- IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
- >;
- };
-
- pinctrl_lpuart6: lpuart6grp {
- fsl,pins = <
- IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
- IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
- IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
- IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
- IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
- >;
- };
-
- pinctrl_lpuart7: lpuart7grp {
- fsl,pins = <
- IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
- IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
- IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
- IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
- IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
- IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
- >;
- };
-
- pinctrl_usdhc0_8bit: usdhc0grp_8bit {
- fsl,pins = <
- IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
- IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
- IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
- IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
- IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
- IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
- IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
- IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
- IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
- IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
- IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
- >;
- };
-
- pinctrl_lpi2c7: lpi2c7grp {
- fsl,pins = <
- IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
- IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
- >;
- };
-
- pinctrl_lpspi3: lpspi3grp {
- fsl,pins = <
- IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
- IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
- IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
- IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
- >;
- };
-
- pinctrl_usbotg1_vbus: otg1vbusgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC0__PTC0 0x20000
- >;
- };
-
- pinctrl_usbotg1_id: otg1idgrp {
- fsl,pins = <
- IMX7ULP_PAD_PTC13__USB0_ID 0x10003
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
- IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
- IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
- IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
- IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
- IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
- >;
- };
-
- pinctrl_usdhc1_rst: usdhc1grp_rst {
- fsl,pins = <
- IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
- IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
- IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
- IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
- >;
- };
-
- pinctrl_dsi_hdmi: dsi_hdmi_grp {
- fsl,pins = <
- IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
- >;
- };
- };
-};
-
-&lcdif {
- status = "okay";
- disp-dev = "mipi_dsi_northwest";
- display = <&display0>;
-
- display0: display@0 {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <9200000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <8>;
- hback-porch = <4>;
- hsync-len = <41>;
- vback-porch = <2>;
- vfront-porch = <4>;
- vsync-len = <10>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
- };
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
-};
-
-&lpi2c7 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpi2c7>;
-};
-
-&lpi2c5 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpi2c5>;
- status = "okay";
-};
-&lpspi3 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpspi3>;
- status = "okay";
-
- spidev0: spi@0 {
- reg = <0>;
- compatible = "rohm,dh2228fv";
- spi-max-frequency = <1000000>;
+ reg_vsd_3v3: regulator-vsd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc0_rst>;
+ gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
-&mipi_dsi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
- lcd_panel = "TRULY-WVGA-TFT3P5581E";
- resets = <&mipi_dsi_reset>;
- status = "okay";
-};
-
-&lpuart4 { /* console */
+&lpuart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart4>;
status = "okay";
};
-&lpuart6 { /* BT */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart6>;
- status = "okay";
-};
-
-&lpuart7 { /* Uart test */
+&tpm4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart7>;
- status = "disabled";
-};
-
-&rpmsg{
+ pinctrl-0 = <&pinctrl_pwm0>;
status = "okay";
};
srp-disable;
hnp-disable;
adp-disable;
+ disable-over-current;
status = "okay";
};
-&usbphy1 {
- fsl,tx-d-cal = <88>;
-};
-
&usdhc0 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+ pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- pinctrl-3 = <&pinctrl_usdhc0>;
- cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_vsd_3v3>;
- vqmmc-supply = <&vldo2_reg>;
status = "okay";
};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_pwm0: pwm0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: otg1vbusgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC0__PTC0 0x20000
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
+ >;
+ };
+
+ pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD0__PTD0 0x3
+ >;
+ };
+};
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 - 2018 NXP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
+ * Copyright 2017 NXP
*/
#ifndef __DTS_IMX7ULP_PINFUNC_H
* The pin function ID is a tuple of
* <mux_conf_reg input_reg mux_mode input_val>
*/
-#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V 0x0000 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA0__PTA0 0x0000 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1 0x0000 0x0104 0x3 0x2
-#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B 0x0000 0x01F8 0x4 0x2
-#define IMX7ULP_PAD_PTA0__LPI2C0_SCL 0x0000 0x017C 0x5 0x2
-#define IMX7ULP_PAD_PTA0__TPM0_CLKIN 0x0000 0x01A8 0x6 0x2
-#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK 0x0000 0x01B8 0x7 0x2
-#define IMX7ULP_PAD_PTA0__LLWU0_P0 0x0000 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V 0x0004 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2 0x0004 0x0108 0x3 0x1
-#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA1__LPI2C0_SDA 0x0004 0x0180 0x5 0x1
-#define IMX7ULP_PAD_PTA1__TPM0_CH0 0x0004 0x0138 0x6 0x1
-#define IMX7ULP_PAD_PTA1__I2S0_RX_FS 0x0004 0x01BC 0x7 0x1
-#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V 0x0008 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3 0x0008 0x010C 0x3 0x1
-#define IMX7ULP_PAD_PTA2__LPUART0_TX 0x0008 0x0200 0x4 0x1
-#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ 0x0008 0x0178 0x5 0x1
-#define IMX7ULP_PAD_PTA2__TPM0_CH1 0x0008 0x013C 0x6 0x1
-#define IMX7ULP_PAD_PTA2__I2S0_RXD0 0x0008 0x01DC 0x7 0x1
-#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V 0x000C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA3__PTA3 0x000C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0 0x000C 0x0100 0x3 0x1
-#define IMX7ULP_PAD_PTA3__LPUART0_RX 0x000C 0x01FC 0x4 0x1
-#define IMX7ULP_PAD_PTA3__TPM0_CH2 0x000C 0x0140 0x6 0x1
-#define IMX7ULP_PAD_PTA3__I2S0_RXD1 0x000C 0x01E0 0x7 0x1
-#define IMX7ULP_PAD_PTA3__CMP0_OUT 0x000C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA3__LLWU0_P1 0x000C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA4__ADC1_CH3A 0x0010 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA4__LPSPI0_SIN 0x0010 0x0114 0x3 0x1
-#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B 0x0010 0x0204 0x4 0x1
-#define IMX7ULP_PAD_PTA4__LPI2C1_SCL 0x0010 0x0188 0x5 0x1
-#define IMX7ULP_PAD_PTA4__TPM0_CH3 0x0010 0x0144 0x6 0x1
-#define IMX7ULP_PAD_PTA4__I2S0_MCLK 0x0010 0x01B4 0x7 0x1
-#define IMX7ULP_PAD_PTA5__ADC1_CH3B 0x0014 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT 0x0014 0x0118 0x3 0x1
-#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA5__LPI2C1_SDA 0x0014 0x018C 0x5 0x1
-#define IMX7ULP_PAD_PTA5__TPM0_CH4 0x0014 0x0148 0x6 0x1
-#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01C0 0x7 0x1
-#define IMX7ULP_PAD_PTA6__ADC1_CH4A 0x0018 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA6__LPSPI0_SCK 0x0018 0x0110 0x3 0x1
-#define IMX7ULP_PAD_PTA6__LPUART1_TX 0x0018 0x020C 0x4 0x1
-#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ 0x0018 0x0184 0x5 0x1
-#define IMX7ULP_PAD_PTA6__TPM0_CH5 0x0018 0x014C 0x6 0x1
-#define IMX7ULP_PAD_PTA6__I2S0_TX_FS 0x0018 0x01C4 0x7 0x1
-#define IMX7ULP_PAD_PTA7__ADC1_CH4B 0x001C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA7__PTA7 0x001C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA7__LPUART1_RX 0x001C 0x0208 0x4 0x1
-#define IMX7ULP_PAD_PTA7__TPM1_CH1 0x001C 0x0154 0x6 0x1
-#define IMX7ULP_PAD_PTA7__I2S0_TXD0 0x001C 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA8__ADC1_CH5A 0x0020 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1 0x0020 0x0120 0x3 0x1
-#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B 0x0020 0x0210 0x4 0x1
-#define IMX7ULP_PAD_PTA8__LPI2C2_SCL 0x0020 0x0194 0x5 0x1
-#define IMX7ULP_PAD_PTA8__TPM1_CLKIN 0x0020 0x01AC 0x6 0x1
-#define IMX7ULP_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA9__ADC1_CH5B 0x0024 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2 0x0024 0x0124 0x3 0x1
-#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA9__LPI2C2_SDA 0x0024 0x0198 0x5 0x1
-#define IMX7ULP_PAD_PTA9__TPM1_CH0 0x0024 0x0150 0x6 0x1
-#define IMX7ULP_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3 0x0028 0x0128 0x3 0x1
-#define IMX7ULP_PAD_PTA10__LPUART2_TX 0x0028 0x0218 0x4 0x1
-#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ 0x0028 0x0190 0x5 0x1
-#define IMX7ULP_PAD_PTA10__TPM2_CLKIN 0x0028 0x01F4 0x6 0x1
-#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01B8 0x7 0x1
-#define IMX7ULP_PAD_PTA11__ADC1_CH6B 0x002C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA11__PTA11 0x002C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA11__LPUART2_RX 0x002C 0x0214 0x4 0x1
-#define IMX7ULP_PAD_PTA11__TPM2_CH0 0x002C 0x0158 0x6 0x1
-#define IMX7ULP_PAD_PTA11__I2S0_RX_FS 0x002C 0x01BC 0x7 0x2
-#define IMX7ULP_PAD_PTA12__ADC1_CH7A 0x0030 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA12__LPSPI1_SIN 0x0030 0x0130 0x3 0x1
-#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B 0x0030 0x021C 0x4 0x1
-#define IMX7ULP_PAD_PTA12__LPI2C3_SCL 0x0030 0x01A0 0x5 0x1
-#define IMX7ULP_PAD_PTA12__TPM2_CH1 0x0030 0x015C 0x6 0x1
-#define IMX7ULP_PAD_PTA12__I2S0_RXD0 0x0030 0x01DC 0x7 0x2
-#define IMX7ULP_PAD_PTA13__ADC1_CH7B 0x0034 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA13__PTA13 0x0034 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT 0x0034 0x0134 0x3 0x2
-#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA13__LPI2C3_SDA 0x0034 0x01A4 0x5 0x2
-#define IMX7ULP_PAD_PTA13__TPM3_CLKIN 0x0034 0x01B0 0x6 0x1
-#define IMX7ULP_PAD_PTA13__I2S0_RXD1 0x0034 0x01E0 0x7 0x2
-#define IMX7ULP_PAD_PTA13__CMP0_OUT 0x0034 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA13__LLWU0_P2 0x0034 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA14__ADC1_CH8A 0x0038 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA14__PTA14 0x0038 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA14__LPSPI1_SCK 0x0038 0x012C 0x3 0x2
-#define IMX7ULP_PAD_PTA14__LPUART3_TX 0x0038 0x0224 0x4 0x2
-#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ 0x0038 0x019C 0x5 0x2
-#define IMX7ULP_PAD_PTA14__TPM3_CH0 0x0038 0x0160 0x6 0x1
-#define IMX7ULP_PAD_PTA14__I2S0_MCLK 0x0038 0x01B4 0x7 0x2
-#define IMX7ULP_PAD_PTA14__LLWU0_P3 0x0038 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA15__ADC1_CH8B 0x003C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA15__PTA15 0x003C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0 0x003C 0x011C 0x3 0x1
-#define IMX7ULP_PAD_PTA15__LPUART3_RX 0x003C 0x0220 0x4 0x1
-#define IMX7ULP_PAD_PTA15__TPM3_CH1 0x003C 0x0164 0x6 0x1
-#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK 0x003C 0x01C0 0x7 0x2
-#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V 0x0040 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT 0x0040 0x0118 0x3 0x2
-#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B 0x0040 0x01F8 0x4 0x1
-#define IMX7ULP_PAD_PTA16__LPI2C0_SCL 0x0040 0x017C 0x5 0x1
-#define IMX7ULP_PAD_PTA16__TPM3_CH2 0x0040 0x0168 0x6 0x1
-#define IMX7ULP_PAD_PTA16__I2S0_TX_FS 0x0040 0x01C4 0x7 0x2
-#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V 0x0044 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA17__LPSPI0_SCK 0x0044 0x0110 0x3 0x2
-#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA17__LPI2C0_SDA 0x0044 0x0180 0x5 0x2
-#define IMX7ULP_PAD_PTA17__TPM3_CH3 0x0044 0x016C 0x6 0x1
-#define IMX7ULP_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V 0x0048 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA18__PTA18 0x0048 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA18__FXIO0_D2 0x0048 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0 0x0048 0x0100 0x3 0x2
-#define IMX7ULP_PAD_PTA18__LPUART0_TX 0x0048 0x0200 0x4 0x2
-#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ 0x0048 0x0178 0x5 0x2
-#define IMX7ULP_PAD_PTA18__TPM3_CH4 0x0048 0x0170 0x6 0x1
-#define IMX7ULP_PAD_PTA18__I2S0_TXD1 0x0048 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA18__LLWU0_P4 0x0048 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V 0x004C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA19__PTA19 0x004C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA19__FXIO0_D3 0x004C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA19__LPUART0_RX 0x004C 0x01FC 0x4 0x2
-#define IMX7ULP_PAD_PTA19__TPM3_CH5 0x004C 0x0174 0x6 0x1
-#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK 0x004C 0x01CC 0x7 0x1
-#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3 0x004C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA19__LLWU0_P5 0x004C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA20__ADC0_CH10A 0x0050 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA20__LPSPI0_SIN 0x0050 0x0114 0x3 0x2
-#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B 0x0050 0x0204 0x4 0x2
-#define IMX7ULP_PAD_PTA20__LPI2C1_SCL 0x0050 0x0188 0x5 0x2
-#define IMX7ULP_PAD_PTA20__TPM0_CLKIN 0x0050 0x01A8 0x6 0x1
-#define IMX7ULP_PAD_PTA20__I2S1_RX_FS 0x0050 0x01D0 0x7 0x1
-#define IMX7ULP_PAD_PTA21__ADC0_CH10B 0x0054 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1 0x0054 0x0104 0x3 0x1
-#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA21__LPI2C1_SDA 0x0054 0x018C 0x5 0x2
-#define IMX7ULP_PAD_PTA21__TPM0_CH0 0x0054 0x0138 0x6 0x2
-#define IMX7ULP_PAD_PTA21__I2S1_RXD0 0x0054 0x01E4 0x7 0x1
-#define IMX7ULP_PAD_PTA22__ADC0_CH9A 0x0058 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2 0x0058 0x0108 0x3 0x2
-#define IMX7ULP_PAD_PTA22__LPUART1_TX 0x0058 0x020C 0x4 0x2
-#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ 0x0058 0x0184 0x5 0x2
-#define IMX7ULP_PAD_PTA22__TPM0_CH1 0x0058 0x013C 0x6 0x2
-#define IMX7ULP_PAD_PTA22__I2S1_RXD1 0x0058 0x01E8 0x7 0x1
-#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTA23__ADC0_CH9B 0x005C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA23__PTA23 0x005C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA23__FXIO0_D7 0x005C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3 0x005C 0x010C 0x3 0x2
-#define IMX7ULP_PAD_PTA23__LPUART1_RX 0x005C 0x0208 0x4 0x2
-#define IMX7ULP_PAD_PTA23__TPM0_CH2 0x005C 0x0140 0x6 0x2
-#define IMX7ULP_PAD_PTA23__I2S1_MCLK 0x005C 0x01C8 0x7 0x1
-#define IMX7ULP_PAD_PTA23__LLWU0_P6 0x005C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTA24__ADC0_CH8A 0x0060 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1 0x0060 0x0120 0x3 0x2
-#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B 0x0060 0x0210 0x4 0x2
-#define IMX7ULP_PAD_PTA24__LPI2C2_SCL 0x0060 0x0194 0x5 0x2
-#define IMX7ULP_PAD_PTA24__TPM0_CH3 0x0060 0x0144 0x6 0x2
-#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK 0x0060 0x01D4 0x7 0x1
-#define IMX7ULP_PAD_PTA25__ADC0_CH8B 0x0064 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2 0x0064 0x0124 0x3 0x2
-#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA25__LPI2C2_SDA 0x0064 0x0198 0x5 0x2
-#define IMX7ULP_PAD_PTA25__TPM0_CH4 0x0064 0x0148 0x6 0x2
-#define IMX7ULP_PAD_PTA25__I2S1_TX_FS 0x0064 0x01D8 0x7 0x1
-#define IMX7ULP_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3 0x0068 0x0128 0x3 0x2
-#define IMX7ULP_PAD_PTA26__LPUART2_TX 0x0068 0x0218 0x4 0x2
-#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ 0x0068 0x0190 0x5 0x2
-#define IMX7ULP_PAD_PTA26__TPM0_CH5 0x0068 0x014C 0x6 0x2
-#define IMX7ULP_PAD_PTA26__I2S1_RXD2 0x0068 0x01EC 0x7 0x1
-#define IMX7ULP_PAD_PTA27__PTA27 0x006C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA27__JTAG_TDO 0x006C 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTA27__FXIO0_D11 0x006C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA27__LPUART2_RX 0x006C 0x0214 0x4 0x2
-#define IMX7ULP_PAD_PTA27__TPM1_CH1 0x006C 0x0154 0x6 0x2
-#define IMX7ULP_PAD_PTA27__I2S1_RXD3 0x006C 0x01F0 0x7 0x1
-#define IMX7ULP_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA28__LPSPI1_SIN 0x0070 0x0130 0x3 0x2
-#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B 0x0070 0x021C 0x4 0x2
-#define IMX7ULP_PAD_PTA28__LPI2C3_SCL 0x0070 0x01A0 0x5 0x2
-#define IMX7ULP_PAD_PTA28__TPM1_CLKIN 0x0070 0x01AC 0x6 0x2
-#define IMX7ULP_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT 0x0074 0x0134 0x3 0x1
-#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTA29__LPI2C3_SDA 0x0074 0x01A4 0x5 0x1
-#define IMX7ULP_PAD_PTA29__TPM1_CH0 0x0074 0x0150 0x6 0x2
-#define IMX7ULP_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA30__ADC0_CH1A 0x0078 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA30__LPSPI1_SCK 0x0078 0x012C 0x3 0x1
-#define IMX7ULP_PAD_PTA30__LPUART3_TX 0x0078 0x0224 0x4 0x1
-#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ 0x0078 0x019C 0x5 0x1
-#define IMX7ULP_PAD_PTA30__TPM2_CLKIN 0x0078 0x01F4 0x6 0x2
-#define IMX7ULP_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTA31__ADC0_CH1B 0x007C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTA31__PTA31 0x007C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTA31__FXIO0_D15 0x007C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0 0x007C 0x011C 0x3 0x2
-#define IMX7ULP_PAD_PTA31__LPUART3_RX 0x007C 0x0220 0x4 0x2
-#define IMX7ULP_PAD_PTA31__TPM2_CH0 0x007C 0x0158 0x6 0x2
-#define IMX7ULP_PAD_PTA31__I2S1_TXD1 0x007C 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1 0x007C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTA31__EWM_IN 0x007C 0x0228 0xc 0x1
-#define IMX7ULP_PAD_PTA31__LLWU0_P7 0x007C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB0__LPSPI0_SIN 0x0080 0x0114 0x3 0x3
-#define IMX7ULP_PAD_PTB0__LPUART0_TX 0x0080 0x0200 0x4 0x3
-#define IMX7ULP_PAD_PTB0__TPM2_CH1 0x0080 0x015C 0x6 0x2
-#define IMX7ULP_PAD_PTB0__CLKOUT0 0x0080 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTB1__ADC0_CH0B 0x0084 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB1__PTB1 0x0084 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB1__FXIO0_D17 0x0084 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT 0x0084 0x0118 0x3 0x3
-#define IMX7ULP_PAD_PTB1__LPUART0_RX 0x0084 0x01FC 0x4 0x3
-#define IMX7ULP_PAD_PTB1__TPM3_CLKIN 0x0084 0x01B0 0x6 0x3
-#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK 0x0084 0x01D4 0x7 0x2
-#define IMX7ULP_PAD_PTB1__RTC_CLKOUT 0x0084 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB1__EWM_IN 0x0084 0x0228 0xc 0x2
-#define IMX7ULP_PAD_PTB1__LLWU0_P8 0x0084 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB2__ADC0_CH6A 0x0088 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB2__LPSPI0_SCK 0x0088 0x0110 0x3 0x3
-#define IMX7ULP_PAD_PTB2__LPUART1_TX 0x0088 0x020C 0x4 0x3
-#define IMX7ULP_PAD_PTB2__TPM3_CH0 0x0088 0x0160 0x6 0x2
-#define IMX7ULP_PAD_PTB2__I2S1_TX_FS 0x0088 0x01D8 0x7 0x2
-#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB3__ADC0_CH6B 0x008C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB3__PTB3 0x008C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB3__FXIO0_D19 0x008C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0 0x008C 0x0100 0x3 0x3
-#define IMX7ULP_PAD_PTB3__LPUART1_RX 0x008C 0x0208 0x4 0x3
-#define IMX7ULP_PAD_PTB3__TPM3_CH1 0x008C 0x0164 0x6 0x2
-#define IMX7ULP_PAD_PTB3__I2S1_TXD0 0x008C 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTB3__TRACE_D0 0x008C 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2 0x008C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB3__LLWU0_P9 0x008C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1 0x0090 0x0104 0x3 0x3
-#define IMX7ULP_PAD_PTB4__LPUART2_TX 0x0090 0x0218 0x4 0x3
-#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ 0x0090 0x0178 0x5 0x3
-#define IMX7ULP_PAD_PTB4__TPM3_CH2 0x0090 0x0168 0x6 0x2
-#define IMX7ULP_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTB4__QSPIA_DATA7 0x0090 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB4__SEC_VIO_B 0x0090 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2 0x0094 0x0108 0x3 0x3
-#define IMX7ULP_PAD_PTB5__LPUART2_RX 0x0094 0x0214 0x4 0x3
-#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ 0x0094 0x0184 0x5 0x3
-#define IMX7ULP_PAD_PTB5__TPM3_CH3 0x0094 0x016C 0x6 0x2
-#define IMX7ULP_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTB5__QSPIA_DATA6 0x0094 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB5__RTC_CLKOUT 0x0094 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB6__ADC1_CH1A 0x0098 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB6__PTB6 0x0098 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB6__FXIO0_D22 0x0098 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3 0x0098 0x010C 0x3 0x3
-#define IMX7ULP_PAD_PTB6__LPUART3_TX 0x0098 0x0224 0x4 0x3
-#define IMX7ULP_PAD_PTB6__LPI2C0_SCL 0x0098 0x017C 0x5 0x3
-#define IMX7ULP_PAD_PTB6__TPM3_CH4 0x0098 0x0170 0x6 0x2
-#define IMX7ULP_PAD_PTB6__I2S1_TXD3 0x0098 0x0000 0x7 0x0
-#define IMX7ULP_PAD_PTB6__QSPIA_DATA5 0x0098 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB6__TRACE_D3 0x0098 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB6__LLWU0_P10 0x0098 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB7__ADC1_CH1B 0x009C 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB7__PTB7 0x009C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB7__FXIO0_D23 0x009C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB7__LPSPI1_SIN 0x009C 0x0130 0x3 0x3
-#define IMX7ULP_PAD_PTB7__LPUART3_RX 0x009C 0x0220 0x4 0x3
-#define IMX7ULP_PAD_PTB7__LPI2C0_SDA 0x009C 0x0180 0x5 0x3
-#define IMX7ULP_PAD_PTB7__TPM3_CH5 0x009C 0x0174 0x6 0x2
-#define IMX7ULP_PAD_PTB7__I2S1_MCLK 0x009C 0x01C8 0x7 0x2
-#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x009C 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB7__CMP1_OUT 0x009C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB7__LLWU0_P11 0x009C 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 0x00A0 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB8__PTB8 0x00A0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB8__FXIO0_D24 0x00A0 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT 0x00A0 0x0134 0x3 0x3
-#define IMX7ULP_PAD_PTB8__LPI2C1_SCL 0x00A0 0x0188 0x5 0x3
-#define IMX7ULP_PAD_PTB8__TPM0_CLKIN 0x00A0 0x01A8 0x6 0x3
-#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK 0x00A0 0x01CC 0x7 0x2
-#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x00A0 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB8__RTC_CLKOUT 0x00A0 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 0x00A4 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB9__PTB9 0x00A4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB9__FXIO0_D25 0x00A4 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB9__LPSPI1_SCK 0x00A4 0x012C 0x3 0x3
-#define IMX7ULP_PAD_PTB9__LPI2C1_SDA 0x00A4 0x018C 0x5 0x3
-#define IMX7ULP_PAD_PTB9__TPM0_CH0 0x00A4 0x0138 0x6 0x3
-#define IMX7ULP_PAD_PTB9__I2S1_RX_FS 0x00A4 0x01D0 0x7 0x2
-#define IMX7ULP_PAD_PTB9__QSPIA_DQS 0x00A4 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB9__LLWU0_P12 0x00A4 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB10__CMP0_IN1 0x00A8 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB10__PTB10 0x00A8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB10__FXIO0_D26 0x00A8 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0 0x00A8 0x011C 0x3 0x3
-#define IMX7ULP_PAD_PTB10__LPI2C2_SCL 0x00A8 0x0194 0x5 0x3
-#define IMX7ULP_PAD_PTB10__TPM0_CH1 0x00A8 0x013C 0x6 0x3
-#define IMX7ULP_PAD_PTB10__I2S1_RXD0 0x00A8 0x01E4 0x7 0x2
-#define IMX7ULP_PAD_PTB10__TRACE_D4 0x00A8 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB11__CMP0_IN3 0x00AC 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB11__PTB11 0x00AC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB11__FXIO0_D27 0x00AC 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1 0x00AC 0x0120 0x3 0x3
-#define IMX7ULP_PAD_PTB11__LPI2C2_SDA 0x00AC 0x0198 0x5 0x3
-#define IMX7ULP_PAD_PTB11__TPM1_CLKIN 0x00AC 0x01AC 0x6 0x3
-#define IMX7ULP_PAD_PTB11__I2S1_RXD1 0x00AC 0x01E8 0x7 0x2
-#define IMX7ULP_PAD_PTB11__TRACE_D5 0x00AC 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 0x00B0 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB12__PTB12 0x00B0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB12__FXIO0_D28 0x00B0 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2 0x00B0 0x0124 0x3 0x3
-#define IMX7ULP_PAD_PTB12__LPUART2_TX 0x00B0 0x0218 0x4 0x4
-#define IMX7ULP_PAD_PTB12__LPI2C3_SCL 0x00B0 0x01A0 0x5 0x3
-#define IMX7ULP_PAD_PTB12__TPM1_CH0 0x00B0 0x0150 0x6 0x3
-#define IMX7ULP_PAD_PTB12__I2S1_RXD2 0x00B0 0x01EC 0x7 0x2
-#define IMX7ULP_PAD_PTB12__TRACE_D6 0x00B0 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 0x00B4 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB13__PTB13 0x00B4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB13__FXIO0_D29 0x00B4 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3 0x00B4 0x0128 0x3 0x3
-#define IMX7ULP_PAD_PTB13__LPUART2_RX 0x00B4 0x0214 0x4 0x4
-#define IMX7ULP_PAD_PTB13__LPI2C3_SDA 0x00B4 0x01A4 0x5 0x3
-#define IMX7ULP_PAD_PTB13__TPM1_CH1 0x00B4 0x0154 0x6 0x3
-#define IMX7ULP_PAD_PTB13__I2S1_RXD3 0x00B4 0x01F0 0x7 0x2
-#define IMX7ULP_PAD_PTB13__QSPIA_DATA4 0x00B4 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB13__TRACE_D7 0x00B4 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTB14__ADC1_CH2A 0x00B8 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB14__PTB14 0x00B8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB14__FXIO0_D30 0x00B8 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ 0x00B8 0x0190 0x5 0x3
-#define IMX7ULP_PAD_PTB14__TPM2_CLKIN 0x00B8 0x01F4 0x6 0x3
-#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x00B8 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B 0x00B8 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTB14__RTC_CLKOUT 0x00B8 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTB14__LLWU0_P13 0x00B8 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB15__ADC1_CH2B 0x00BC 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB15__PTB15 0x00BC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB15__FXIO0_D31 0x00BC 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ 0x00BC 0x019C 0x5 0x3
-#define IMX7ULP_PAD_PTB15__TPM2_CH0 0x00BC 0x0158 0x6 0x3
-#define IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x00BC 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB16__ADC0_CH4A 0x00C0 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB16__PTB16 0x00C0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB16__TPM2_CH1 0x00C0 0x015C 0x6 0x3
-#define IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x00C0 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB16__LLWU0_P14 0x00C0 0x0000 0xd 0x0
-#define IMX7ULP_PAD_PTB17__ADC0_CH4B 0x00C4 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB17__PTB17 0x00C4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB17__TPM3_CLKIN 0x00C4 0x01B0 0x6 0x2
-#define IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x00C4 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB18__ADC0_CH5A 0x00C8 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB18__PTB18 0x00C8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB18__TPM3_CH0 0x00C8 0x0160 0x6 0x3
-#define IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x00C8 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB19__ADC0_CH5B 0x00CC 0x0000 0x0 0x0
-#define IMX7ULP_PAD_PTB19__PTB19 0x00CC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTB19__TPM3_CH1 0x00CC 0x0164 0x6 0x3
-#define IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x00CC 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTB19__USB0_ID 0x00CC 0x0338 0xa 0x0
-#define IMX7ULP_PAD_PTB19__LLWU0_P15 0x00CC 0x0000 0xd 0x0
+
#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027C 0x5 0x1
+#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024C 0x4 0x1
+#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTC3__PTC3 0x000C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000C 0x0248 0x4 0x1
-#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000C 0x0288 0x6 0x1
-#define IMX7ULP_PAD_PTC3__FB_AD3 0x000C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
+#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
+#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
-#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02A0 0x3 0x1
+#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
-#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02BC 0x5 0x1
-#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028C 0x6 0x1
+#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
+#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
-#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02A4 0x3 0x1
+#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02C0 0x5 0x1
+#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020C 0x2 0x1
-#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02A8 0x3 0x1
+#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
+#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
-#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02B8 0x5 0x1
+#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTC7__PTC7 0x001C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001C 0x0210 0x2 0x1
-#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001C 0x0254 0x4 0x1
-#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001C 0x02C8 0x6 0x1
-#define IMX7ULP_PAD_PTC7__FB_AD7 0x001C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
+#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
+#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
+#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
-#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02B0 0x3 0x1
-#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025C 0x4 0x1
-#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02FC 0x5 0x1
-#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02CC 0x6 0x1
+#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
+#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
+#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
+#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
-#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02B4 0x3 0x1
+#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
-#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02C4 0x6 0x1
+#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021C 0x2 0x1
-#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02AC 0x3 0x1
+#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
+#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
-#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02F8 0x5 0x1
-#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02E8 0x6 0x1
+#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
+#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTC11__PTC11 0x002C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002C 0x0220 0x2 0x1
-#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002C 0x029C 0x3 0x1
-#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002C 0x0260 0x4 0x1
-#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002C 0x02EC 0x6 0x1
-#define IMX7ULP_PAD_PTC11__FB_AD11 0x002C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
+#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
+#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
+#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
+#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
-#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02F0 0x6 0x1
+#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030C 0x5 0x1
-#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02F4 0x6 0x1
+#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
+#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1
#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022C 0x2 0x1
-#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031C 0x3 0x1
+#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
+#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
-#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02DC 0x6 0x1
+#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTC15__PTC15 0x003C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003C 0x0230 0x2 0x1
-#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003C 0x026C 0x4 0x1
-#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003C 0x02E0 0x6 0x1
-#define IMX7ULP_PAD_PTC15__FB_AD15 0x003C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
+#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
+#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
+#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
-#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02E4 0x6 0x1
+#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1
#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
-#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02D8 0x6 0x1
+#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023C 0x2 0x1
+#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
-#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02D0 0x6 0x1
+#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2
-#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033C 0xc 0x1
-#define IMX7ULP_PAD_PTC19__PTC19 0x004C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004C 0x0240 0x2 0x1
-#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004C 0x0310 0x3 0x1
-#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004C 0x02D4 0x6 0x1
-#define IMX7ULP_PAD_PTC19__FB_A16 0x004C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTC19__USB0_ID 0x004C 0x0338 0xa 0x3
-#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTC19__VIU_DE 0x004C 0x033C 0xc 0x3
+#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1
+#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
+#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
+#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
+#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3
+#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3
#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD3__PTD3 0x008C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD7__PTD7 0x009C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009C 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD8__PTD8 0x00A0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00A0 0x0298 0x6 0x2
-#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00A0 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD9__PTD9 0x00A4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00A4 0x0280 0x6 0x2
-#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00A4 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD10__PTD10 0x00A8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00A8 0x0284 0x6 0x2
-#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00A8 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTD11__PTD11 0x00AC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00AC 0x0288 0x6 0x2
-#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00AC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
+#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
+#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
+#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
+#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02A0 0x3 0x2
+#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02A4 0x3 0x2
+#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027C 0x5 0x2
+#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02A8 0x3 0x2
-#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024C 0x4 0x2
+#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
+#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTE3__PTE3 0x010C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010C 0x0248 0x4 0x2
-#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010C 0x02C8 0x6 0x2
-#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
+#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
+#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02B0 0x3 0x2
+#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
-#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02BC 0x5 0x2
-#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02CC 0x6 0x2
+#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
+#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02B4 0x3 0x2
+#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02C0 0x5 0x2
-#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02C4 0x6 0x2
+#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
+#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033C 0xc 0x2
+#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2
#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02AC 0x3 0x2
+#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
-#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02B8 0x5 0x2
-#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02E8 0x6 0x2
+#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
+#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1
-#define IMX7ULP_PAD_PTE7__PTE7 0x011C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011C 0x029C 0x3 0x2
-#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011C 0x0254 0x4 0x2
-#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011C 0x02EC 0x6 0x2
-#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011C 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTE7__FB_A18 0x011C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011C 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTE7__VIU_FID 0x011C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
+#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
+#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
+#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
-#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025C 0x4 0x2
-#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02FC 0x5 0x2
-#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02F0 0x6 0x2
+#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
+#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
+#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
-#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02F4 0x6 0x2
-#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032C 0x7 0x1
+#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
+#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031C 0x3 0x2
+#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
-#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02F8 0x5 0x2
-#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02DC 0x6 0x2
+#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
+#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE11__PTE11 0x012C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012C 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE11__VIU_D19 0x012C 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012C 0x0260 0x4 0x2
-#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012C 0x02E0 0x6 0x2
-#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0
-#define IMX7ULP_PAD_PTE11__FB_A20 0x012C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
+#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
+#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
+#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
-#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02E4 0x6 0x2
+#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
-#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030C 0x5 0x2
-#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02D8 0x6 0x2
-#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032C 0x8 0x2
+#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
+#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
+#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
+#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
-#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02D0 0x6 0x2
+#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
-#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTE15__PTE15 0x013C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013C 0x0000 0x2 0x0
-#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013C 0x0310 0x3 0x2
-#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013C 0x026C 0x4 0x2
-#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013C 0x02D4 0x6 0x2
-#define IMX7ULP_PAD_PTE15__FB_A24 0x013C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013C 0x0000 0xa 0x0
-#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013C 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTE15__VIU_D23 0x013C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
+#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
+#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
+#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0
#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033C 0xc 0x0
#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027C 0x5 0x3
+#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024C 0x4 0x3
+#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF3__PTF3 0x018C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018C 0x0248 0x4 0x3
-#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018C 0x0288 0x6 0x3
-#define IMX7ULP_PAD_PTF3__FB_AD16 0x018C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
+#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
+#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
-#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02A0 0x3 0x3
+#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
-#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02BC 0x5 0x3
-#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028C 0x6 0x2
+#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
+#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
-#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02A4 0x3 0x3
+#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02C0 0x5 0x3
+#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020C 0x2 0x2
-#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02A8 0x3 0x3
+#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
+#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
-#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02B8 0x5 0x3
+#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF7__PTF7 0x019C 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019C 0x0210 0x2 0x2
-#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019C 0x0254 0x4 0x3
-#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019C 0x02C8 0x6 0x3
-#define IMX7ULP_PAD_PTF7__FB_AD20 0x019C 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF7__VIU_D3 0x019C 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF8__PTF8 0x01A0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01A0 0x0214 0x2 0x2
-#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01A0 0x02B0 0x3 0x3
-#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01A0 0x025C 0x4 0x3
-#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01A0 0x02FC 0x5 0x3
-#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01A0 0x02CC 0x6 0x3
-#define IMX7ULP_PAD_PTF8__FB_AD21 0x01A0 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF8__USB1_CLK 0x01A0 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF8__VIU_D4 0x01A0 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF9__PTF9 0x01A4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01A4 0x0218 0x2 0x2
-#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01A4 0x02B4 0x3 0x3
-#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01A4 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01A4 0x0300 0x5 0x3
-#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01A4 0x02C4 0x6 0x3
-#define IMX7ULP_PAD_PTF9__FB_AD22 0x01A4 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF9__USB1_NXT 0x01A4 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF9__VIU_D5 0x01A4 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF10__PTF10 0x01A8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01A8 0x021C 0x2 0x2
-#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01A8 0x02AC 0x3 0x3
-#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01A8 0x0264 0x4 0x3
-#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01A8 0x02F8 0x5 0x3
-#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01A8 0x02E8 0x6 0x3
-#define IMX7ULP_PAD_PTF10__FB_AD23 0x01A8 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF10__USB1_STP 0x01A8 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF10__VIU_D6 0x01A8 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF11__PTF11 0x01AC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01AC 0x0220 0x2 0x2
-#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01AC 0x029C 0x3 0x3
-#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01AC 0x0260 0x4 0x3
-#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01AC 0x02EC 0x6 0x3
-#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01AC 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF11__USB1_DIR 0x01AC 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF11__VIU_D7 0x01AC 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF12__PTF12 0x01B0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01B0 0x0224 0x2 0x2
-#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01B0 0x0314 0x3 0x3
-#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01B0 0x0268 0x4 0x3
-#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01B0 0x0308 0x5 0x3
-#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01B0 0x02F0 0x6 0x3
-#define IMX7ULP_PAD_PTF12__FB_AD24 0x01B0 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF12__USB1_DATA0 0x01B0 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF12__VIU_D8 0x01B0 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF13__PTF13 0x01B4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01B4 0x0228 0x2 0x2
-#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01B4 0x0318 0x3 0x3
-#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01B4 0x0000 0x4 0x0
-#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01B4 0x030C 0x5 0x3
-#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01B4 0x02F4 0x6 0x3
-#define IMX7ULP_PAD_PTF13__FB_AD25 0x01B4 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF13__USB1_DATA1 0x01B4 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF13__VIU_D9 0x01B4 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF14__PTF14 0x01B8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01B8 0x022C 0x2 0x2
-#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01B8 0x031C 0x3 0x3
-#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01B8 0x0270 0x4 0x3
-#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01B8 0x0304 0x5 0x3
-#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01B8 0x02DC 0x6 0x3
-#define IMX7ULP_PAD_PTF14__FB_AD26 0x01B8 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF14__USB1_DATA2 0x01B8 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF14__VIU_D10 0x01B8 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF15__PTF15 0x01BC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01BC 0x0230 0x2 0x2
-#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01BC 0x026C 0x4 0x3
-#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01BC 0x02E0 0x6 0x3
-#define IMX7ULP_PAD_PTF15__FB_AD27 0x01BC 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF15__USB1_DATA3 0x01BC 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF15__VIU_D11 0x01BC 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF16__PTF16 0x01C0 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF16__USB1_DATA4 0x01C0 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF16__VIU_D12 0x01C0 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01C0 0x0234 0x2 0x2
-#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01C0 0x0324 0x3 0x3
-#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01C0 0x02E4 0x6 0x3
-#define IMX7ULP_PAD_PTF16__FB_AD28 0x01C0 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF17__PTF17 0x01C4 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF17__USB1_DATA5 0x01C4 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF17__VIU_D13 0x01C4 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01C4 0x0238 0x2 0x2
-#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01C4 0x0328 0x3 0x3
-#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01C4 0x02D8 0x6 0x3
-#define IMX7ULP_PAD_PTF17__FB_AD29 0x01C4 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF18__PTF18 0x01C8 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF18__USB1_DATA6 0x01C8 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF18__VIU_D14 0x01C8 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01C8 0x023C 0x2 0x2
-#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01C8 0x0320 0x3 0x3
-#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01C8 0x02D0 0x6 0x3
-#define IMX7ULP_PAD_PTF18__FB_AD30 0x01C8 0x0000 0x9 0x0
-#define IMX7ULP_PAD_PTF19__PTF19 0x01CC 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF19__USB1_DATA7 0x01CC 0x0000 0xb 0x0
-#define IMX7ULP_PAD_PTF19__VIU_D15 0x01CC 0x0000 0xc 0x0
-#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01CC 0x0240 0x2 0x2
-#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01CC 0x0310 0x3 0x3
-#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01CC 0x02D4 0x6 0x3
-#define IMX7ULP_PAD_PTF19__FB_AD31 0x01CC 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
+#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
+#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
+#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
+#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
+#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
+#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
+#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
+#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
+#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
+#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
+#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
+#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
+#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
+#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
+#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
+#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
+#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
+#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
+#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
+#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
+#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
+#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
+#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
+#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
+#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
+#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
+#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
+#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
+#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
+#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
+#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
+#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
+#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
+#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
+#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
+#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
+#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
+#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
+#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
+#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
+#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
+#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
+#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
+#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
+#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
+#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
+#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
+#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
+#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
+#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
#endif /* __DTS_IMX7ULP_PINFUNC_H */
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2015-2016 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx7ulp-clock.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "imx7ulp-pinfunc.h"
/ {
interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
aliases {
- gpio0 = &gpio4;
- gpio1 = &gpio5;
- gpio2 = &gpio0;
- gpio3 = &gpio1;
- gpio4 = &gpio2;
- gpio5 = &gpio3;
+ gpio0 = &gpio_ptc;
+ gpio1 = &gpio_ptd;
+ gpio2 = &gpio_pte;
+ gpio3 = &gpio_ptf;
+ i2c0 = &lpi2c6;
+ i2c1 = &lpi2c7;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
serial0 = &lpuart4;
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
- usb0 = &usbotg1;
- i2c4 = &lpi2c4;
- i2c5 = &lpi2c5;
- i2c6 = &lpi2c6;
- i2c7 = &lpi2c7;
- spi0 = &qspi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
- reg = <0>;
- };
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /* global autoconfigured region for contiguous allocations */
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0xC000000>;
- alignment = <0x2000>;
- linux,cma-default;
- };
-
- rpmsg_reserved: rpmsg@9FFF0000 {
- no-map;
- reg = <0x9FF00000 0x100000>;
+ reg = <0xf00>;
};
-
};
intc: interrupt-controller@40021000 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x40021000 0x1000>,
- <0x40022000 0x100>;
+ <0x40022000 0x1000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ckil: clock@0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "ckil";
- };
-
- osc: clock@1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "osc";
- };
-
- sirc: clock@2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <16000000>;
- clock-output-names = "sirc";
- };
+ rosc: clock-rosc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "rosc";
+ #clock-cells = <0>;
+ };
- firc: clock@3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- clock-output-names = "firc";
- };
+ sosc: clock-sosc {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "sosc";
+ #clock-cells = <0>;
+ };
- upll: clock@4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <480000000>;
- clock-output-names = "upll";
- };
+ sirc: clock-sirc {
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-output-names = "sirc";
+ #clock-cells = <0>;
+ };
- mpll: clock@5 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <480000000>;
- clock-output-names = "mpll";
- };
+ firc: clock-firc {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ clock-output-names = "firc";
+ #clock-cells = <0>;
};
- sram: sram@20000000 {
- compatible = "fsl,lpm-sram";
- reg = <0x1fffc000 0x4000>;
+ upll: clock-upll {
+ compatible = "fixed-clock";
+ clock-frequency = <480000000>;
+ clock-output-names = "upll";
+ #clock-cells = <0>;
};
- ahbbridge0: ahb-bridge0@40000000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ ahbbridge0: bus@40000000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x800000>;
ranges;
- edma0: dma-controller@40080000 {
+ edma1: dma-controller@40080000 {
#dma-cells = <2>;
- compatible = "nxp,imx7ulp-edma";
+ compatible = "fsl,imx7ulp-edma";
reg = <0x40080000 0x2000>,
<0x40210000 0x1000>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dma", "dmamux0";
- clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
- };
-
- mu: mu@40220000 {
- compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
- reg = <0x40220000 0x1000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
- };
-
- nmi: nmi@40220000 {
- compatible = "fsl,imx7ulp-nmi";
- reg = <0x40220000 0x1000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
- };
-
- rpmsg: rpmsg{
- compatible = "fsl,imx7ulp-rpmsg";
- memory-region = <&rpmsg_reserved>;
- status = "disabled";
- };
-
- snvs: snvs@40230000 {
- compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
- reg = <0x40230000 0x10000>;
-
- snvs_rtc: snvs-rtc-lp{
- compatible = "fsl,sec-v4.0-mon-rtc-lp";
- regmap =<&snvs>;
- offset = <0x34>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "snvs-rtc";
- clocks = <&clks IMX7ULP_CLK_SNVS>;
- };
+ clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
+ <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
};
crypto: crypto@40240000 {
#size-cells = <1>;
reg = <0x40240000 0x10000>;
ranges = <0 0x40240000 0x10000>;
- clocks = <&clks IMX7ULP_CLK_CAAM>,
- <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
+ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "aclk", "ipg";
sec_jr0: jr@1000 {
};
};
- tpm5: tpm@40260000 {
- compatible = "fsl,imx7ulp-tpm";
- reg = <0x40260000 0x1000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPTPM5>;
- };
-
- lpit: 1@40270000 {
- compatible = "fsl,imx-lpit";
- reg = <0x40270000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- /* clocks = <&lpclk>;*/
- clocks = <&clks IMX7ULP_CLK_LPIT1>;
- assigned-clock-rates = <48000000>;
- assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- };
-
- lpi2c4: lpi2c4@402B0000 {
- compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x402B0000 0x10000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPI2C4>;
- clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpi2c5: lpi2c4@402C0000 {
- compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x402C0000 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPI2C5>;
- clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpspi2: lpspi@40290000 {
- compatible = "fsl,imx7ulp-spi";
- reg = <0x40290000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPSPI2>;
- clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpspi3: lpspi@402A0000 {
- compatible = "fsl,imx7ulp-spi";
- reg = <0x402A0000 0x10000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPSPI3>;
- clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpuart4: serial@402D0000 {
+ lpuart4: serial@402d0000 {
compatible = "fsl,imx7ulp-lpuart";
- reg = <0x402D0000 0x1000>;
+ reg = <0x402d0000 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPUART4>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
- lpuart5: serial@402E0000 {
+ lpuart5: serial@402e0000 {
compatible = "fsl,imx7ulp-lpuart";
- reg = <0x402E0000 0x1000>;
+ reg = <0x402e0000 0x1000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPUART5>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
- dmas = <&edma0 0 20>, <&edma0 0 19>;
- dma-names = "tx","rx";
status = "disabled";
};
+ tpm4: pwm@40250000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x40250000 0x1000>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&pcc2 IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
+
usbotg1: usb@40330000 {
- compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
- "fsl,imx27-usb";
+ compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x40330000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_USB0>;
- fsl,usbphy = <&usbphy1>;
+ clocks = <&pcc2 IMX7ULP_CLK_USB0>;
+ phys = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
};
usbmisc1: usbmisc@40330200 {
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
- compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
- "fsl,imx6q-usbmisc";
reg = <0x40330200 0x200>;
};
- usbphy1: usbphy@0x40350000 {
- compatible = "fsl,imx7ulp-usbphy",
- "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+ usbphy1: usb-phy@40350000 {
+ compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
reg = <0x40350000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_USB_PHY>;
- nxp,sim = <&sim>;
+ clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
+ #phy-cells = <0>;
};
- usdhc0: usdhc@40370000 {
- compatible = "fsl,imx7ulp-usdhc";
+ usdhc0: mmc@40370000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
reg = <0x40370000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&clks IMX7ULP_CLK_NIC1_DIV>,
- <&clks IMX7ULP_CLK_USDHC0>;
- clock-names ="ipg", "ahb", "per";
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC0>;
+ clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
- usdhc1: usdhc@40380000 {
- compatible = "fsl,imx7ulp-usdhc";
+ usdhc1: mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
- <&clks IMX7ULP_CLK_NIC1_DIV>,
- <&clks IMX7ULP_CLK_USDHC1>;
- clock-names ="ipg", "ahb", "per";
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
- wdog1: wdog@403D0000 {
- compatible = "fsl,imx7ulp-wdt";
- reg = <0x403D0000 0x10000>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_WDG1>;
- assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
- assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
- /*
- * As the 1KHz LPO clock rate is not trimed,the actually clock
- * is about 667Hz, so the init timeout 60s should set 40*1000
- * in the TOVAL register.
- */
- timeout-sec = <40>;
+ scg1: clock-controller@403e0000 {
+ compatible = "fsl,imx7ulp-scg1";
+ reg = <0x403e0000 0x10000>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll";
+ #clock-cells = <1>;
};
- wdog2: wdog@40430000 {
+ wdog1: watchdog@403d0000 {
compatible = "fsl,imx7ulp-wdt";
- reg = <0x40430000 0x10000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_WDG2>;
- assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
- assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
+ reg = <0x403d0000 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
- clks: scg1@403E0000 {
- compatible = "fsl,imx7ulp-scg1";
- reg = <0x403E0000 0x10000>;
- clocks = <&ckil>, <&osc>, <&sirc>,
- <&firc>, <&upll>, <&mpll>;
- clock-names = "ckil", "osc", "sirc",
- "firc", "upll", "mpll";
+ pcc2: clock-controller@403f0000 {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f0000 0x10000>;
#clock-cells = <1>;
- assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
- <&clks IMX7ULP_CLK_USDHC1>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
- <&clks IMX7ULP_CLK_NIC1_DIV>;
- };
-
- pcc2: pcc2@403F0000 {
- compatible = "fsl,imx7ulp-pcc2";
- reg = <0x403F0000 0x10000>;
- };
-
- pmc1: pmc1@40400000 {
- compatible = "fsl,imx7ulp-pmc1";
- reg = <0x40400000 0x1000>;
- };
-
- smc1: smc1@40410000 {
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk",
+ "firc_bus_clk", "rosc", "spll_bus_clk";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ };
+
+ smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+ <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+ clock-names = "divcore", "hsrun_divcore";
};
+ pcc3: clock-controller@40b30000 {
+ compatible = "fsl,imx7ulp-pcc3";
+ reg = <0x40b30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk",
+ "firc_bus_clk", "rosc", "spll_bus_clk";
+ };
};
- ahbbridge1: ahb-bridge1@40800000 {
- compatible = "fsl,aips-bus", "simple-bus";
+ ahbbridge1: bus@40800000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40800000 0x800000>;
ranges;
- lpi2c6: lpi2c6@40A40000 {
+ lpi2c6: i2c@40a40000 {
compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x40A40000 0x10000>;
+ reg = <0x40a40000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPI2C6>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
- lpi2c7: lpi2c7@40A50000 {
+ lpi2c7: i2c@40a50000 {
compatible = "fsl,imx7ulp-lpi2c";
- reg = <0x40A50000 0x10000>;
+ reg = <0x40a50000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPI2C7>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
- lpuart6: serial@40A60000 {
+ lpuart6: serial@40a60000 {
compatible = "fsl,imx7ulp-lpuart";
- reg = <0x40A60000 0x1000>;
+ reg = <0x40a60000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPUART6>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
- dmas = <&edma0 0 22>, <&edma0 0 21>;
- dma-names = "tx","rx";
status = "disabled";
};
- lpuart7: serial@40A70000 {
+ lpuart7: serial@40a70000 {
compatible = "fsl,imx7ulp-lpuart";
- reg = <0x40A70000 0x1000>;
+ reg = <0x40a70000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_LPUART7>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
clock-names = "ipg";
- assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
- assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
- assigned-clock-rates = <50000000>;
- dmas = <&edma0 0 24>, <&edma0 0 23>;
- dma-names = "tx","rx";
- status = "disabled";
- };
-
- lcdif: lcdif@40AA0000 {
- compatible = "fsl,imx7ulp-lcdif";
- reg = <0x40aa0000 0x10000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_DUMMY>,
- <&clks IMX7ULP_CLK_LCDIF>,
- <&clks IMX7ULP_CLK_DUMMY>;
- clock-names = "axi", "pix", "disp_axi";
- status = "disabled";
- };
-
- mipi_dsi: mipi_dsi@40A90000 {
- compatible = "fsl,imx7ulp-mipi-dsi";
- reg = <0x40A90000 0x10000>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_DSI>;
- clock-names = "mipi_dsi_clk";
- sim = <&sim>;
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
status = "disabled";
};
- mmdc: mmdc@40ab0000 {
- compatible = "fsl,imx7ulp-mmdc";
- reg = <0x40ab0000 0x4000>;
+ memory-controller@40ab0000 {
+ compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x40ab0000 0x1000>;
+ clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
};
- pcc3: pcc3@40B30000 {
- compatible = "fsl,imx7ulp-pcc3";
- reg = <0x40B30000 0x10000>;
- };
-
- iomuxc: iomuxc@4103D000 {
- compatible = "fsl,imx7ulp-iomuxc-0";
- reg = <0x4103D000 0x1000>;
- fsl,mux_mask = <0xf00>;
- status = "disabled";
- };
-
- iomuxc1: iomuxc1@40ac0000 {
- compatible = "fsl,imx7ulp-iomuxc-1";
+ iomuxc1: pinctrl@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
- fsl,mux_mask = <0xf00>;
};
- gpio4: gpio@4103f000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x4103f000 0x1000 0x4100F000 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&iomuxc 0 0 32>;
- };
-
- gpio5: gpio@41040000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x41040000 0x1000 0x4100F040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&iomuxc 0 32 32>;
- };
-
- gpio0: gpio@40ae0000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
+ gpio_ptc: gpio@40ae0000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc1 0 0 32>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLC>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 0 20>;
};
- gpio1: gpio@40af0000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x40af0000 0x1000 0x400F0040 0x40>;
+ gpio_ptd: gpio@40af0000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40af0000 0x1000 0x400f0040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc1 0 32 32>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLD>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 32 12>;
};
- gpio2: gpio@40b00000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x40b00000 0x1000 0x400F0080 0x40>;
+ gpio_pte: gpio@40b00000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40b00000 0x1000 0x400f0080 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc1 0 64 32>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLE>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 64 16>;
};
- gpio3: gpio@40b10000 {
- compatible = "fsl,imx7ulp-gpio";
- reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
+ gpio_ptf: gpio@40b10000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc1 0 96 32>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLF>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 96 20>;
};
+ };
- pmc0: pmc0@410a1000 {
- compatible = "fsl,imx7ulp-pmc0";
- reg = <0x410a1000 0x1000>;
- };
+ m4aips1: bus@41080000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x41080000 0x80000>;
+ ranges;
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};
- qspi1: qspi@410A5000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7ulp-qspi";
- reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7ULP_CLK_DUMMY>,
- <&clks IMX7ULP_CLK_DUMMY>;
- clock-names = "qspi_en", "qspi";
- status = "disabled";
- };
-
- gpu: gpu@41800000 {
- compatible = "fsl,imx6q-gpu";
- reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
- <0x60000000 0x40000000>, <0x0 0x4000000>;
- reg-names = "iobase_3d", "iobase_2d",
- "phys_baseaddr", "contiguous_mem";
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_3d", "irq_2d";
- clocks = <&clks IMX7ULP_CLK_GPU3D>,
- <&clks IMX7ULP_CLK_NIC1_DIV>,
- <&clks IMX7ULP_CLK_GPU_DIV>,
- <&clks IMX7ULP_CLK_GPU2D>,
- <&clks IMX7ULP_CLK_NIC1_DIV>,
- <&clks IMX7ULP_CLK_NIC1_DIV>;
- clock-names = "gpu3d_clk", "gpu3d_shader_clk",
- "gpu3d_axi_clk", "gpu2d_clk",
- "gpu2d_shader_clk", "gpu2d_axi_clk";
+ ocotp: efuse@410a6000 {
+ compatible = "fsl,imx7ulp-ocotp", "syscon";
+ reg = <0x410a6000 0x4000>;
+ clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
};
};
-
- imx_ion {
- compatible = "fsl,mxc-ion";
- fsl,heap-id = <0>;
- };
};
};
};
+&aips4 {
+ u-boot,dm-spl;
+};
+
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
u-boot,dm-spl;
};
+&usbmisc1 {
+ u-boot,dm-spl;
+};
+
+&usbphynop1 {
+ u-boot,dm-spl;
+};
+
+&usbotg1 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
u-boot,dm-spl;
};
-
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
&i2c2 {
status = "okay";
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&iomuxc {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
};
&pinctrl_ecspi1 {
&pinctrl_pmic {
u-boot,dm-spl;
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
- /* Disable Pullup for SD_VSEL */
- MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
- >;
};
&pinctrl_uart3 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-bl-common-u-boot.dtsi"
+
+&iomuxc {
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-osm-s.dtsi"
+
+/ {
+ model = "Kontron BL i.MX8MM OSM-S (N802X S)";
+ compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
+
+ aliases {
+ ethernet1 = &usbnet;
+ };
+
+ /* fixed crystal dedicated to mcp2542fd */
+ osc_can: clock-osc-can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "osc-can";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "led3";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm2 0 5000 0>;
+ };
+
+ reg_rst_eth2: regulator-rst-eth2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth2>;
+ gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-name = "rst-usb-eth2";
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
+ gpio = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "usb1-vbus";
+ };
+
+ reg_vdd_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vdd-5v";
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp251xfd";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&osc_can>;
+ interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
+ /*
+ * Limit the SPI clock to 15 MHz to prevent issues
+ * with corrupted data due to chip errata.
+ */
+ spi-max-frequency = <15000000>;
+ vdd-supply = <®_vdd_3v3>;
+ xceiver-supply = <®_vdd_5v>;
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ eeram@0 {
+ compatible = "microchip,48l640";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-connection-type = "rgmii-rxid";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ reg = <0>;
+ reset-assert-us = <1>;
+ reset-deassert-us = <15000>;
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>;
+ gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out",
+ "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+ gpio-line-names = "", "", "dio4-in", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ disable-over-current;
+ vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbnet: ethernet@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
+ >;
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ >;
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
+ >;
+ };
+
+ pinctrl_reg_usb1_vbus: regusb1vbusgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usb_eth2: usbeth2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-bl-common-u-boot.dtsi"
+
+&iomuxc {
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Touch Reset */
+ >;
+ };
+};
/dts-v1/;
-#include "imx8mm-kontron-n801x-som.dtsi"
+#include "imx8mm-kontron-sl.dtsi"
/ {
- model = "Kontron i.MX8MM N801X S";
- compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+ model = "Kontron BL i.MX8MM (N801X S)";
+ compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-#include "imx8mm-kontron-n801x-u-boot.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-#include "imx8mm-kontron-n801x-s.dts"
-
-/ {
- model = "Kontron i.MX8MM N801X S LVDS";
- compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
- power-supply = <®_vdd_24v>;
- brightness-levels = <0 100>;
- num-interpolated-steps = <100>;
- default-brightness-level = <100>;
- status = "okay";
- };
-
- reg_panel_pwr: regpanel-pwr {
- compatible = "regulator-fixed";
- regulator-name = "reg_panel_pwr";
- regulator-always-on;
- gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_panel_rst: regpanel-rst {
- compatible = "regulator-fixed";
- regulator-name = "reg_panel_rst";
- regulator-always-on;
- gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_panel_stby: regpanel-stby {
- compatible = "regulator-fixed";
- regulator-name = "reg_panel_stby";
- regulator-always-on;
- gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_panel_hinv: regpanel-hinv {
- compatible = "regulator-fixed";
- regulator-name = "reg_panel_hinv";
- regulator-always-on;
- gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_panel_vinv: regpanel-vinv {
- compatible = "regulator-fixed";
- regulator-name = "reg_panel_vinv";
- gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vdd_24v: regulator-24v {
- compatible = "regulator-fixed";
- regulator-name = "reg-vdd-24v";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- regulator-boot-on;
- regulator-always-on;
- status = "okay";
- };
-};
-
-&i2c2 {
- status = "okay";
-
- gt911@5d {
- compatible = "goodix,gt928";
- reg = <0x5d>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch>;
- interrupt-parent = <&gpio3>;
- interrupts = <22 8>;
- reset-gpios = <&gpio3 23 0>;
- irq-gpios = <&gpio3 22 0>;
- };
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- #pwm-cells = <2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_panel: panelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
- MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
- MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
- >;
- };
-
- pinctrl_pwm1: pwm1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
- >;
- };
-
- pinctrl_touch: touchgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
- MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
- >;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Kontron Electronics GmbH
- */
-
-#include "imx8mm-kontron-n801x-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Kontron OSM-S i.MX8MM (N802X SOM)";
+ compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ /*
+ * There are multiple SoM flavors with different DDR sizes.
+ * The smallest is 1GB. For larger sizes the bootloader will
+ * update the reg property.
+ */
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x1e0000>;
+ };
+
+ partition@1e0000 {
+ label = "env";
+ reg = <0x1e0000 0x10000>;
+ };
+
+ partition@1f0000 {
+ label = "env_redundant";
+ reg = <0x1f0000 0x10000>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "+0V8_VDD_SOC (BUCK1)";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <850000>;
+ nxp,dvs-standby-voltage = <800000>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "+0V9_VDD_ARM (BUCK2)";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_dram: BUCK3 {
+ regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "+3V3 (BUCK4)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-name = "+1V8 (BUCK5)";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_snvs: LDO1 {
+ regulator-name = "+1V8_NVCC_SNVS (LDO1)";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_snvs: LDO2 {
+ regulator-name = "+0V8_VDD_SNVS (LDO2)";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdda: LDO3 {
+ regulator-name = "+1V8_VDDA (LDO3)";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_phy: LDO4 {
+ regulator-name = "+0V9_VDD_PHY (LDO4)";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_sd: LDO5 {
+ regulator-name = "NVCC_SD (LDO5)";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ rtc@52 {
+ compatible = "microcrystal,rv3028";
+ reg = <0x52>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
+ trickle-diode-disable;
+ };
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
#include "imx8mm.dtsi"
/ {
- model = "Kontron i.MX8MM N801X SoM";
- compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
+ model = "Kontron SL i.MX8MM (N801X SOM)";
+ compatible = "kontron,imx8mm-sl", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x1e0000>;
+ };
+
+ partition@1e0000 {
+ label = "env";
+ reg = <0x1e0000 0x10000>;
+ };
+
+ partition@1f0000 {
+ label = "env_redundant";
+ reg = <0x1f0000 0x10000>;
+ };
+ };
};
};
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators {
reg_vdd_soc: BUCK1 {
- regulator-name = "buck1";
+ regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
};
reg_vdd_arm: BUCK2 {
- regulator-name = "buck2";
+ regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
};
reg_vdd_dram: BUCK3 {
- regulator-name = "buck3";
+ regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
};
reg_vdd_3v3: BUCK4 {
- regulator-name = "buck4";
+ regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
reg_vdd_1v8: BUCK5 {
- regulator-name = "buck5";
+ regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
reg_nvcc_dram: BUCK6 {
- regulator-name = "buck6";
+ regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
};
reg_nvcc_snvs: LDO1 {
- regulator-name = "ldo1";
+ regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
reg_vdd_snvs: LDO2 {
- regulator-name = "ldo2";
+ regulator-name = "+0V8_VDD_SNVS (LDO2)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
};
reg_vdda: LDO3 {
- regulator-name = "ldo3";
+ regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
reg_vdd_phy: LDO4 {
- regulator-name = "ldo4";
+ regulator-name = "+0V9_VDD_PHY (LDO4)";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
};
reg_nvcc_sd: LDO5 {
- regulator-name = "ldo5";
+ regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
- MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
>;
};
/ {
chosen {
- stdout-path = &uart2;
+ stdout-path = &uart1;
};
aliases {
};
};
+&aips4 {
+ u-boot,dm-spl;
+};
+
&i2c4 {
/delete-node/ codec@1a;
};
-&pinctrl_uart1 {
- /delete-property/ u-boot,dm-spl;
+®_usb_otg1_vbus {
+ u-boot,dm-spl;
};
-&pinctrl_uart2 {
+&usbmisc1 {
u-boot,dm-spl;
};
-&uart1 {
- /delete-property/ u-boot,dm-spl;
+&usbphynop1 {
+ u-boot,dm-spl;
};
-&uart2 {
+&usbotg1 {
u-boot,dm-spl;
};
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
line-name = "dig2_out#";
};
+ dig2ctl {
+ gpio-hog;
+ output-low;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ line-name = "dig2_ctl";
+ };
+
+ dig1ctl {
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "dig1_ctl";
+ };
+
dig1out {
gpio-hog;
output-high;
};
&gpio2 {
- gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
+ gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
"dig1_out#", "dig1_in", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
+ MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include "imx8mm-venice-u-boot.dtsi"
+
+&gpio1 {
+ rs232en {
+ gpio-hog;
+ output-low;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ line-name = "rs232_en#";
+ };
+};
+
+&gpio5 {
+ pci_wdis {
+ gpio-hog;
+ output-high;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ line-name = "pci_wdis#";
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <300>;
+};
+
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7904 i.MX8MM board";
+ compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-0 {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ key-1 {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-2 {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ key-3 {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ key-4 {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led01_yel";
+ gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led02_yel";
+ gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led03_yel";
+ gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led04_yel";
+ gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led05_yel";
+ gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-10 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-11 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-12 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led07_grn";
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-13 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led07_red";
+ gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-14 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led08_grn";
+ gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-15 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led08_yel";
+ gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-16 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led09_grn";
+ gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-17 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led09_yel";
+ gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-18 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led10_grn";
+ gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-19 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_YELLOW>;
+ label = "led10_yel";
+ gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&gpio1 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "rs232_en#", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "pci_wdis#", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <700000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_0p9";
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_soc";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_arm";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_1p8";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ gpioled: gpio@27 {
+ compatible = "nxp,pca9555";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+/* off-board RS232 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* off-board RS232 */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pcie0: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
+#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
u-boot,dm-spl;
};
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
&gpio1 {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&iomuxc {
- u-boot,dm-spl;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
&pca6416_0 {
compatible = "ti,tca6416";
};
u-boot,off-on-delay-us = <20000>;
};
-&spba1 {
- u-boot,dm-spl;
-};
-
&uart2 {
u-boot,dm-spl;
};
mmc-hs400-enhanced-strobe;
};
-&wdog1 {
- u-boot,dm-spl;
-};
-
&pinctrl_wdog {
u-boot,dm-spl;
};
-
-&binman {
- u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
- };
-
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SYS_TEXT_BASE>;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x960000>;
- entry = <0x960000>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- default = "conf";
-
- conf {
- description = "NAME";
- firmware = "uboot";
- loadables = "atf";
- fdt = "fdt";
- };
- };
- };
- };
-
- imx-boot {
- filename = "flash.bin";
- pad-byte = <0x00>;
-
- spl: blob-ext@1 {
- offset = <0x0>;
- filename = "spl.bin";
- };
-
- uboot: blob-ext@2 {
- offset = <0x58000>;
- filename = "u-boot.itb";
- };
- };
-};
* Copyright 2021 BSH Hausgeraete GmbH
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
+#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
u-boot,dm-spl;
};
-&aips1 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&aips4 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
&gpio1 {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&iomuxc {
- u-boot,dm-spl;
-};
-
-&osc_24m {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
-
-&binman {
- u-boot-spl-ddr {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
-
- ddr-1d-imem-fw {
- filename = "ddr3_imem_1d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-1d-dmem-fw {
- filename = "ddr3_dmem_1d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
- };
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
- fit,fdt-list = "of-list";
- #address-cells = <1>;
-
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_SYS_TEXT_BASE>;
- type = "standalone";
-
- uboot_blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
- };
- };
-
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x960000>;
- load = <0x960000>;
- type = "firmware";
-
- atf_blob {
- filename = "bl31.bin";
- type = "atf-bl31";
- };
- };
-
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
-
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
-
- uboot_fdt_blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
- };
- };
- };
-
- configurations {
- default = "@config-DEFAULT-SEQ";
-
- binman_configuration: @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
- loadables = "atf";
- };
- };
- };
- };
-
- imx-boot {
- filename = "flash.bin";
- pad-byte = <0x00>;
-
- spl {
- filename = "spl.bin";
- offset = <0x0>;
- type = "blob-ext";
- };
-
- binman_uboot: uboot {
- filename = "u-boot.itb";
- offset = <0x58000>;
- type = "blob-ext";
- };
- };
-};
* Copyright 2019, 2021 NXP
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&spba1 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
+#include "imx8mn-u-boot.dtsi"
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
-
-&wdog1 {
- u-boot,dm-spl;
-};
-
-&binman {
- u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- ddr-1d-imem-fw {
- filename = "ddr4_imem_1d_201810.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-1d-dmem-fw {
- filename = "ddr4_dmem_1d_201810.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-imem-fw {
- filename = "ddr4_imem_2d_201810.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-dmem-fw {
- filename = "ddr4_dmem_2d_201810.bin";
- type = "blob-ext";
- align-end = <4>;
- };
- };
-
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SYS_TEXT_BASE>;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x960000>;
- entry = <0x960000>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- default = "conf";
-
- conf {
- description = "NAME";
- firmware = "uboot";
- loadables = "atf";
- fdt = "fdt";
- };
- };
- };
- };
-
- imx-boot {
- filename = "flash.bin";
- pad-byte = <0x00>;
-
- spl: blob-ext@1 {
- offset = <0x0>;
- filename = "spl.bin";
- };
-
- uboot: blob-ext@2 {
- offset = <0x58000>;
- filename = "u-boot.itb";
- };
- };
-};
&pinctrl_pmic {
u-boot,dm-spl;
};
-
-&binman {
- u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
-
- u-boot-spl {
- align-end = <4>;
- };
-
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
-
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- type = "blob-ext";
- align-end = <4>;
- };
- };
-
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SYS_TEXT_BASE>;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x960000>;
- entry = <0x960000>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- default = "conf";
-
- conf {
- description = "NAME";
- firmware = "uboot";
- loadables = "atf";
- fdt = "fdt";
- };
- };
- };
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&aips4 {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&spba1 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ ddr-1d-imem-fw {
+#ifdef CONFIG_IMX8M_LPDDR4
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+#elif CONFIG_IMX8M_DDR4
+ filename = "ddr4_imem_1d.bin";
+#else
+ filename = "ddr3_imem_1d.bin";
+#endif
+ type = "blob-ext";
+ align-end = <4>;
+ };
+
+ ddr-1d-dmem-fw {
+#ifdef CONFIG_IMX8M_LPDDR4
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+#elif CONFIG_IMX8M_DDR4
+ filename = "ddr4_dmem_1d.bin";
+#else
+ filename = "ddr3_dmem_1d.bin";
+#endif
+ type = "blob-ext";
+ align-end = <4>;
+ };
+
+ ddr-2d-imem-fw {
+#ifdef CONFIG_IMX8M_LPDDR4
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+#elif CONFIG_IMX8M_DDR4
+ filename = "ddr4_imem_2d.bin";
+#endif
+ type = "blob-ext";
+ align-end = <4>;
+ };
+
+ ddr-2d-dmem-fw {
+#ifdef CONFIG_IMX8M_LPDDR4
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+#elif CONFIG_IMX8M_DDR4
+ filename = "ddr4_dmem_2d.bin";
+#endif
+ type = "blob-ext";
+ align-end = <4>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = <CONFIG_SYS_TEXT_BASE>;
+ type = "standalone";
+
+ uboot-blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x960000>;
+ load = <0x960000>;
+ type = "firmware";
+
+ atf-blob {
+ filename = "bl31.bin";
+ type = "atf-bl31";
+ };
+ };
+
+ binman_fip: fip {
+ arch = "arm64";
+ compression = "none";
+ description = "Trusted Firmware FIP";
+ load = <0x40310000>;
+ type = "firmware";
+ };
+
+ @fdt-SEQ {
+ compression = "none";
+ description = "NAME";
+ type = "flat_dt";
+
+ uboot-fdt-blob {
+ filename = "u-boot.dtb";
+ type = "blob-ext";
+ };
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+
+ binman_configuration: @config-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "uboot";
+ loadables = "atf";
+ };
+ };
+ };
+ };
+
+ imx-boot {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+#ifdef CONFIG_FSPI_CONF_HEADER
+ fspi_conf_block {
+ filename = CONFIG_FSPI_CONF_FILE;
+ type = "blob-ext";
+ offset = <0x400>;
+ };
+
+ spl {
+ filename = "spl.bin";
+ offset = <0x1000>;
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ filename = "u-boot.itb";
+ offset = <0x59000>;
+ type = "blob-ext";
+ };
+#else
+
+ spl {
+ offset = <0x0>;
+ filename = "spl.bin";
+ type = "blob-ext";
+ };
+
+ binman_uboot: uboot {
+ offset = <0x58000>;
+ filename = "u-boot.itb";
+ type = "blob-ext";
+ };
+#endif
+ };
+};
* Copyright 2021 Collabora Ltd.
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
+#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
u-boot,dm-spl;
};
-&aips1 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&aips4 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
&gpio1 {
u-boot,dm-spl;
};
u-boot,dm-spl;
};
-&iomuxc {
- u-boot,dm-spl;
-};
-
-&osc_24m {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
-
-&wdog1 {
- u-boot,dm-spl;
-};
-
-&binman {
- u-boot-spl-ddr {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
-
- ddr-1d-imem-fw {
- filename = "ddr4_imem_1d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-1d-dmem-fw {
- filename = "ddr4_dmem_1d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-2d-imem-fw {
- filename = "ddr4_imem_2d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-2d-dmem-fw {
- filename = "ddr4_dmem_2d.bin";
- align-end = <4>;
- type = "blob-ext";
- };
- };
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
- fit,fdt-list = "of-list";
- #address-cells = <1>;
-
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_SYS_TEXT_BASE>;
- type = "standalone";
-
- uboot_blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
- };
- };
-
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x960000>;
- load = <0x960000>;
- type = "firmware";
-
- atf_blob {
- filename = "bl31.bin";
- type = "atf-bl31";
- };
- };
-
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
-
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
-
- uboot_fdt_blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
- };
- };
- };
-
- configurations {
- default = "@config-DEFAULT-SEQ";
-
- binman_configuration: @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
- loadables = "atf";
- };
- };
- };
- };
-
- imx-boot {
- filename = "flash.bin";
- pad-byte = <0x00>;
-
- spl {
- filename = "spl.bin";
- offset = <0x0>;
- type = "blob-ext";
- };
-
- binman_uboot: uboot {
- filename = "u-boot.itb";
- offset = <0x58000>;
- type = "blob-ext";
- };
- };
-};
* Copyright 2022 Gateworks Corporation
*/
-/ {
- binman: binman {
- multiple-images;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- u-boot,dm-spl;
- };
-};
-
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&spba1 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
+#include "imx8mn-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
u-boot,dm-spl;
};
-&wdog1 {
- u-boot,dm-spl;
-};
-
&pinctrl_wdog {
u-boot,dm-spl;
};
-
-&binman {
- u-boot-spl-ddr {
- align = <4>;
- align-size = <4>;
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
-
- u-boot-spl {
- align-end = <4>;
- filename = "u-boot-spl.bin";
- };
-
- ddr-1d-imem-fw {
- filename = "lpddr4_pmu_train_1d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-1d-dmem-fw {
- filename = "lpddr4_pmu_train_1d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-2d-imem-fw {
- filename = "lpddr4_pmu_train_2d_imem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
-
- ddr-2d-dmem-fw {
- filename = "lpddr4_pmu_train_2d_dmem.bin";
- align-end = <4>;
- type = "blob-ext";
- };
- };
-
- spl {
- filename = "spl.bin";
-
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
- fit,fdt-list = "of-list";
- #address-cells = <1>;
-
- images {
- uboot {
- arch = "arm64";
- compression = "none";
- description = "U-Boot (64-bit)";
- load = <CONFIG_SYS_TEXT_BASE>;
- type = "standalone";
-
- uboot_blob {
- filename = "u-boot-nodtb.bin";
- type = "blob-ext";
- };
- };
-
- atf {
- arch = "arm64";
- compression = "none";
- description = "ARM Trusted Firmware";
- entry = <0x960000>;
- load = <0x960000>;
- type = "firmware";
-
- atf_blob {
- filename = "bl31.bin";
- type = "blob-ext";
- };
- };
-
- binman_fip: fip {
- arch = "arm64";
- compression = "none";
- description = "Trusted Firmware FIP";
- load = <0x40310000>;
- type = "firmware";
- };
-
- @fdt-SEQ {
- compression = "none";
- description = "NAME";
- type = "flat_dt";
-
- uboot_fdt_blob {
- filename = "u-boot.dtb";
- type = "blob-ext";
- };
- };
- };
-
- configurations {
- default = "@config-DEFAULT-SEQ";
-
- binman_configuration: @config-SEQ {
- description = "NAME";
- fdt = "fdt-SEQ";
- firmware = "uboot";
- loadables = "atf";
- };
- };
- };
- };
-
- imx-boot {
- filename = "flash.bin";
- pad-byte = <0x00>;
-
- spl {
- filename = "spl.bin";
- offset = <0x0>;
- type = "blob-ext";
- };
-
- binman_uboot: uboot {
- filename = "u-boot.itb";
- offset = <0x58000>;
- type = "blob-ext";
- };
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&i2c4 {
+ u-boot,dm-spl;
+};
+
+&i2c5 {
+ u-boot,dm-spl;
+};
+
+&i2c6 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ no-1-8-v;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&eqos {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <100000>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-icore-mx8mp.dtsi"
+#include <dt-bindings/usb/pd.h>
+
+/ {
+ model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
+ "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb1_host_vbus";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ };
+};
+
+/* Ethernet */
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,led-mode = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SDCARD */
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ pinctrl-names = "default" ;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
+ MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_reg_usb1: regusb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+ compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450c";
+ interrupt-parent = <&gpio3>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x25>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "BUCK1";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1025000>;
+ regulator-min-microvolt = <720000>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3600000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-name = "BUCK4";
+ };
+
+ buck5: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-name = "BUCK5";
+ };
+
+ buck6: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1155000>;
+ regulator-min-microvolt = <1045000>;
+ regulator-name = "BUCK6";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-name = "LDO1";
+ };
+
+ ldo3: LDO3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1890000>;
+ regulator-min-microvolt = <1710000>;
+ regulator-name = "LDO3";
+ };
+
+ ldo5: LDO5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "LDO5";
+ };
+ };
+ };
+};
+
+/* EMMC */
+&usdhc3 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+};
m2_dis2_hog {
gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_gdis#";
};
m2rst_hog {
gpio-hog;
- gpios = <6 GPIO_ACTIVE_LOW>;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_rst#";
};
m2_off_hog {
gpio-hog;
- gpios = <14 GPIO_ACTIVE_LOW>;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_off#";
};
m2_dis1_hog {
gpio-hog;
- gpios = <18 GPIO_ACTIVE_LOW>;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_wdis#";
};
- uart_rs485_hog {
+ rs485_en {
gpio-hog;
- gpios = <31 GPIO_ACTIVE_LOW>;
+ gpios = <31 GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "uart_rs485";
+ line-name = "rs485_en";
};
};
&gpio5 {
u-boot,dm-spl;
- uart_half_hog {
+ rs485_half {
gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "uart_half";
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rs485_hd";
};
- uart_term_hog {
+ rs485_term {
gpio-hog;
- gpios = <1 GPIO_ACTIVE_LOW>;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "uart_term";
+ line-name = "rs485_term";
};
};
};
+&crypto {
+ u-boot,dm-spl;
+};
+
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
u-boot,dm-spl;
};
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&uart3 {
u-boot,dm-spl;
};
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header providing constants for i.MX28 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MXS_PINCTRL_H__
#include <asm/armv8/sec_firmware.h>
struct icid_id_table {
+#ifndef CONFIG_SPL_BUILD
const char *compat;
- u32 id;
- u32 reg;
phys_addr_t compat_addr;
+#endif
phys_addr_t reg_addr;
+ u32 reg;
+#ifndef CONFIG_SPL_BUILD
+ u32 id;
+#endif
bool le;
};
void set_icids(void);
void fdt_fixup_icid(void *blob);
+#ifdef CONFIG_SPL_BUILD
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
+ { .reg = regA, \
+ .reg_addr = addr, \
+ .le = _le \
+ }
+#else
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .compat = name, \
.id = idA, \
.reg_addr = addr, \
.le = _le \
}
+#endif
#ifdef CONFIG_SYS_FSL_SEC_LE
#define SEC_IS_LE true
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
+#define SCFG_SNPCNFGCR_EDMASNP 0x00020000
#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
select IMX8M_LPDDR4
select SUPPORT_SPL
+config TARGET_IMX8MP_ICORE_MX8MP
+ bool "Engicam i.Core MX8M Plus SOM"
+ select BINMAN
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+ help
+ i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP.
+
+ i.Core MX8M Plus EDIMM2.2:
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
+ * i.Core MX8M Plus needs to mount on top of EDIMM2.2 for
+ creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
+
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
select BINMAN
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/dhelectronics/dh_imx8mp/Kconfig"
source "board/engicam/imx8mm/Kconfig"
+source "board/engicam/imx8mp/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
reset@1 {
compatible = "sandbox,reset";
+ u-boot,dm-pre-proper;
};
rng {
reset@0 {
compatible = "sandbox,warm-reset";
+ u-boot,dm-pre-proper;
};
reset@1 {
compatible = "sandbox,reset";
+ u-boot,dm-pre-proper;
};
resetc: reset-ctl {
--- /dev/null
+if TARGET_IMX8MP_ICORE_MX8MP
+
+config SYS_BOARD
+ default "imx8mp"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx8mp_icore_mx8mp"
+
+config IMX_CONFIG
+ default "board/engicam/imx8mp/imximage-lpddr4.cfg"
+
+endif
--- /dev/null
+i.Core-MX8M-Plus-EDIMM2.2
+M: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+M: Matteo Lisi <matteo.lisi@engicam.com>
+S: Maintained
+F: board/engicam/imx8mp
+F: include/configs/imx8mp_icore_mx8mp.h
+F: configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
--- /dev/null
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += icore_mx8mp.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Copyright (C) 2022 Amarula Solutions(India)
+ *
+ * Authors:
+ * Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+ * Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <linux/delay.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Enable RGMII TX clk output */
+ setbits_le32(&gpr->gpr[1], BIT(22));
+}
+
+static int setup_eqos(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
+#if CONFIG_IS_ENABLED(NET)
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER u-boot-spl-ddr.bin 0x920000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x1323 },
+ { 0x3d400024, 0x1e84800 },
+ { 0x3d400064, 0x7a0118 },
+ { 0x3d400070, 0x61027f10 },
+ { 0x3d400074, 0x7b0 },
+ { 0x3d4000d0, 0xc00307a3 },
+ { 0x3d4000d4, 0xc50000 },
+ { 0x3d4000dc, 0xf4003f },
+ { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e8, 0x660048 },
+ { 0x3d4000ec, 0x160048 },
+ { 0x3d400100, 0x2028222a },
+ { 0x3d400104, 0x807bf },
+ { 0x3d40010c, 0xe0e000 },
+ { 0x3d400110, 0x12040a12 },
+ { 0x3d400114, 0x2050f0f },
+ { 0x3d400118, 0x1010009 },
+ { 0x3d40011c, 0x501 },
+ { 0x3d400130, 0x20800 },
+ { 0x3d400134, 0xe100002 },
+ { 0x3d400138, 0x120 },
+ { 0x3d400144, 0xc80064 },
+ { 0x3d400180, 0x3e8001e },
+ { 0x3d400184, 0x3207a12 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x49f820e },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1f0e },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x9121c1c },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
+ { 0x3d400250, 0x1705 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400404, 0x72ff },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x1021 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e8, 0x660048 },
+ { 0x3d4020ec, 0x160048 },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x1021 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e8, 0x660048 },
+ { 0x3d4030ec, 0x160048 },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x18 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x3e8 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x1204a, 0x500 },
+ { 0x1304a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3300 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3300 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xfa0 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x3ff4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x3ff4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xf400 },
+ { 0x54033, 0x333f },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xf400 },
+ { 0x54039, 0x333f },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x48 },
+ { 0x5403c, 0x48 },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x1 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x8 },
+ { 0x90159, 0xe8 },
+ { 0x9015a, 0x109 },
+ { 0x9015b, 0x0 },
+ { 0x9015c, 0x8140 },
+ { 0x9015d, 0x10c },
+ { 0x9015e, 0x10 },
+ { 0x9015f, 0x8138 },
+ { 0x90160, 0x104 },
+ { 0x90161, 0x8 },
+ { 0x90162, 0x448 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0xf },
+ { 0x90165, 0x7c0 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0x0 },
+ { 0x90168, 0xe8 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x47 },
+ { 0x9016b, 0x630 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x618 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0xe0 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x0 },
+ { 0x90174, 0x7c8 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x8140 },
+ { 0x90178, 0x10c },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x478 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x1 },
+ { 0x9017e, 0x8 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x4 },
+ { 0x90181, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x68 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x3 },
+ { 0x2000b, 0x7d },
+ { 0x2000c, 0xfa },
+ { 0x2000d, 0x9c4 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 4000mts 1D */
+ .drate = 4000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 4000mts 2D */
+ .drate = 4000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 4000, 400, 100, },
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Amarula Solutions(India)
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Authors:
+ * Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+ * Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ ret = power_pca9450_init(I2C_PMIC, 0x25);
+ if (ret)
+ printf("power init failed");
+ p = pmic_get("PCA9450");
+ pmic_probe(p);
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+#ifdef CONFIG_IMX8M_LPDDR4
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
+ /* set DVS0 to 0.85v for special case*/
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+#else
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Kernel uses OD/OD freq for SOC */
+ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+#elif defined(CONFIG_IMX8M_DDR4)
+ /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Set NVCC_DRAM to 1.2v for DDR4 */
+ pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
+#endif
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
+ * Should set the clock after PMIC setting done.
+ * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
+ */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ enable_tzc380();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC1;
void spl_board_init(void)
{
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize caam_jr: %d\n", ret);
- }
- puts("Normal Boot\n");
+ arch_misc_init();
}
#ifdef CONFIG_SPL_LOAD_FIT
struct udevice *dev;
int ret;
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize caam_jr: %d\n", ret);
- }
+ arch_misc_init();
+
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
void spl_board_init(void)
{
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- struct udevice *dev;
- int ret;
+ arch_misc_init();
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize caam_jr: %d\n", ret);
- }
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
void cpld_set_nand(void)
{
u16 reg = CPLD_CFG_RCW_SRC_NAND;
+
+ if (CPLD_READ(cpld_ver) > 0x2)
+ reg = CPLD_CFG_RCW_SRC_NAND_4K;
+
u8 reg5 = (u8)(reg >> 1);
u8 reg6 = (u8)(reg & 1);
#define CPLD_BANK_SEL_ALTBANK 0x04
#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
+#define CPLD_CFG_RCW_SRC_NAND_4K 0x118
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif
if (cfg_rcw_src == 0x25)
printf("vBank %d\n", CPLD_READ(vbank));
- else if (cfg_rcw_src == 0x106)
+ else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
return 0;
}
+void nand_fixup(void)
+{
+ u32 csor = 0;
+
+ if (CPLD_READ(pcba_ver) < 0x7)
+ return;
+
+ /* Change NAND Flash PGS/SPRZ configuration */
+ csor = CONFIG_SYS_NAND_CSOR;
+ if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
+ csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
+
+ if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
+ csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
+
+ if (IS_ENABLED(CONFIG_TFABOOT)) {
+ u8 cfg_rcw_src1, cfg_rcw_src2;
+ u16 cfg_rcw_src;
+
+ cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
+ cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
+ cpld_rev_bit(&cfg_rcw_src1);
+ cfg_rcw_src = cfg_rcw_src1;
+ cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
+
+ if (cfg_rcw_src == 0x25)
+ set_ifc_csor(IFC_CS1, csor);
+ else if (cfg_rcw_src == 0x118)
+ set_ifc_csor(IFC_CS0, csor);
+ else
+ printf("Invalid setting\n");
+ } else {
+ if (IS_ENABLED(CONFIG_NAND_BOOT))
+ set_ifc_csor(IFC_CS0, csor);
+ else
+ set_ifc_csor(IFC_CS1, csor);
+ }
+}
+
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
+ /* nand driver fix up */
+ nand_fixup();
+
+ /* fdt fix up */
fdt_fixup_phy_addr(blob);
+
return 0;
}
#endif
ctrl);
gpio_requestf(cfg->gpio_param, "dio%d", i);
gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
- cfg->pwm_padmux) {
+ } else if (hwconfig_subarg_cmp(arg, "mode", "pwm")) {
if (!cfg->pwm_param) {
printf("DIO%d: Error: pwm config invalid\n",
i);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
return 0;
}
-int eeprom_init(int quiet)
+int venice_eeprom_init(int quiet)
{
char rev_pcb;
int rev_bom;
u8 chksum[2]; /* 0x4E */
};
-int eeprom_init(int quiet);
+int venice_eeprom_init(int quiet);
const char *eeprom_get_model(void);
const char *eeprom_get_baseboard_model(void);
const char *eeprom_get_dtb_name(int level, char *buf, int len);
/* Buck 1 DVS control through PMIC_STBY_REQ */
dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- /* Set DVS1 to 0.8v for suspend */
- dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
+ /* Set DVS1 to 0.85v for suspend */
+ dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
- /* increase VDD_DRAM to 0.95v for 3Ghz DDR */
- dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
+ /* increase VDD_SOC to 0.95V before first DRAM access */
+ dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
- /* VDD_DRAM off in suspend: B1_ENMODE=10 */
- dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
-
- /* set VDD_SNVS_0V8 from default 0.85V */
- dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+ /* Kernel uses OD/OD freq for SOC */
+ /* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */
+ dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */
dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
}
else if ((!strncmp(model, "GW7901", 6)) ||
- (!strncmp(model, "GW7902", 6))) {
- if (!strncmp(model, "GW7901", 6))
- ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
- else
+ (!strncmp(model, "GW7902", 6)) ||
+ (!strncmp(model, "GW7903", 6)) ||
+ (!strncmp(model, "GW7904", 6))) {
+ if (!strncmp(model, "GW7902", 6))
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
+ else
+ ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
if (ret) {
printf("PMIC : failed I2C2 probe: %d\n", ret);
return ret;
break;
mdelay(1);
}
- dram_sz = eeprom_init(0);
+ dram_sz = venice_eeprom_init(0);
/* PMIC */
power_init_board();
int board_init(void)
{
- eeprom_init(1);
+ venice_eeprom_init(1);
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx)
M: Frieder Schrempf <frieder.schrempf@kontron.de>
S: Maintained
-F: arch/arm/dts/imx6ul-kontron-n6*
-F: arch/arm/dts/imx6ull-kontron-n6*
+F: arch/arm/dts/imx6ul-kontron-sl*
+F: arch/arm/dts/imx6ul-kontron-bl*
+F: arch/arm/dts/imx6ull-kontron-sl*
+F: arch/arm/dts/imx6ull-kontron-bl*
F: board/kontron/sl-mx6ul
F: configs/kontron-sl-mx6ul_defconfig
F: doc/board/kontron/sl-mx6ul.rst
else
obj-y := sl-mx6ul.o
endif
+
+obj-y += sl-mx6ul-common.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include <asm/types.h>
+#include <asm/arch/sys_proto.h>
+
+#include <sl-mx6ul-common.h>
+
+bool sl_mx6ul_is_spi_nor_boot(void)
+{
+ u32 bmode = imx6_src_get_boot_mode();
+
+ /*
+ * Check if "EEPROM Recovery" enabled and ECSPI2_CONREG not 0x0.
+ * If this is the case and U-Boot didn't initialize the SPI bus
+ * yet, we can safely assume that we are booting from SPI NOR.
+ */
+ if ((bmode & 0x40000000) && readl(0x0200c008))
+ return true;
+
+ return false;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#ifndef __SL_MX6UL_COMMON_H
+#define __SL_MX6UL_COMMON_H
+
+bool sl_mx6ul_is_spi_nor_boot(void);
+
+#endif // __SL_MX6UL_COMMON_H
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
+#include <env_internal.h>
#include <fdt_support.h>
#include <phy.h>
+#include <sl-mx6ul-common.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ if (sl_mx6ul_is_spi_nor_boot() && CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ else if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
+ return ENVL_MMC;
+
+ return ENVL_NOWHERE;
+}
--- /dev/null
+kernel_addr_r=0x82000000
+ramdisk_addr_r=0x88080000
+pxefile_addr_r=0x80100000
+scriptaddr=0x80100000
#include <linux/sizes.h>
#include <linux/errno.h>
#include <mmc.h>
+#include <sl-mx6ul-common.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
- BOARD_TYPE_KTN_N631X = 1,
- BOARD_TYPE_KTN_N641X,
+ BOARD_TYPE_KTN_SL_UL = 1,
+ BOARD_TYPE_KTN_SL_ULL,
BOARD_TYPE_MAX
};
static int do_board_detect(void)
{
if (is_mx6ul())
- gd->board_type = BOARD_TYPE_KTN_N631X;
+ gd->board_type = BOARD_TYPE_KTN_SL_UL;
else if (is_mx6ull())
- gd->board_type = BOARD_TYPE_KTN_N641X;
+ gd->board_type = BOARD_TYPE_KTN_SL_ULL;
printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
/*
* The default boot fuse settings use the SD card (MMC1) as primary
- * boot device, but allow SPI NOR as a fallback boot device.
- * We can't detect the fallback case and spl_boot_device() will return
- * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
- * Therefore we try to load U-Boot proper vom SPI NOR after loading
- * from MMC has failed.
+ * boot device, but allow SPI NOR as a fallback boot device. There
+ * is no proper way to detect if the fallback was used. Therefore
+ * we read the ECSPI2_CONREG register and see if it differs from the
+ * reset value 0x0. If that's the case we can assume that the BootROM
+ * has successfully probed the SPI NOR.
*/
- spl_boot_list[0] = bootdev;
-
switch (bootdev) {
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
- spl_boot_list[1] = BOOT_DEVICE_SPI;
+ if (sl_mx6ul_is_spi_nor_boot()) {
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ return;
+ }
break;
}
+
+ spl_boot_list[0] = bootdev;
}
int board_early_init_f(void)
{
setup_iomux_uart();
- setup_spi();
+ if (sl_mx6ul_is_spi_nor_boot())
+ setup_spi();
return 0;
}
int board_fit_config_name_match(const char *name)
{
- if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
- !strcmp(name, "imx6ul-kontron-n631x-s"))
+ if (gd->board_type == BOARD_TYPE_KTN_SL_UL && is_mx6ul() &&
+ (!strcmp(name, "imx6ul-kontron-n631x-s") || !strcmp(name, "imx6ul-kontron-bl")))
return 0;
- if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
- !strcmp(name, "imx6ull-kontron-n641x-s"))
+ if (gd->board_type == BOARD_TYPE_KTN_SL_ULL && is_mx6ull() &&
+ (!strcmp(name, "imx6ull-kontron-n641x-s") || !strcmp(name, "imx6ull-kontron-bl")))
return 0;
return -1;
Kontron SL/BL i.MX8M Mini Boards (N801x)
M: Frieder Schrempf <frieder.schrempf@kontron.de>
S: Maintained
-F: arch/arm/dts/imx8mm-kontron-n801x-*
+F: arch/arm/dts/imx8mm-kontron*
F: board/kontron/sl-mx8mm
F: configs/kontron-sl-mx8mm_defconfig
F: doc/board/kontron/sl-mx8mm.rst
struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
- {0x3d400304, 0x1},
- {0x3d400030, 0x1},
- {0x3d400000, 0xa3080020},
- {0x3d400020, 0x223},
- {0x3d400024, 0x3a980},
- {0x3d400064, 0x5b0087},
- {0x3d4000d0, 0xc00305ba},
- {0x3d4000d4, 0x940000},
- {0x3d4000dc, 0xd4002d},
- {0x3d4000e0, 0x310000},
- {0x3d4000e8, 0x66004d},
- {0x3d4000ec, 0x16004d},
- {0x3d400100, 0x191e1920},
- {0x3d400104, 0x60630},
- {0x3d40010c, 0xb0b000},
- {0x3d400110, 0xe04080e},
- {0x3d400114, 0x2040c0c},
- {0x3d400118, 0x1010007},
- {0x3d40011c, 0x401},
- {0x3d400130, 0x20600},
- {0x3d400134, 0xc100002},
- {0x3d400138, 0xd8},
- {0x3d400144, 0x96004b},
- {0x3d400180, 0x2ee0017},
- {0x3d400184, 0x2605b8e},
- {0x3d400188, 0x0},
- {0x3d400190, 0x497820a},
- {0x3d400194, 0x80303},
- {0x3d4001b4, 0x170a},
- {0x3d4001a0, 0xe0400018},
- {0x3d4001a4, 0xdf00e4},
- {0x3d4001a8, 0x80000000},
- {0x3d4001b0, 0x11},
- {0x3d4001c0, 0x1},
- {0x3d4001c4, 0x1},
- {0x3d4000f4, 0xc99},
- {0x3d400108, 0x70e1617},
- {0x3d400200, 0x17},
- {0x3d40020c, 0x0},
- {0x3d400210, 0x1f1f},
- {0x3d400204, 0x80808},
- {0x3d400214, 0x7070707},
- {0x3d400218, 0x7070707},
- {0x3d400250, 0x29001701},
- {0x3d400254, 0x2c},
- {0x3d40025c, 0x4000030},
- {0x3d400264, 0x900093e7},
- {0x3d40026c, 0x2005574},
- {0x3d400400, 0x111},
- {0x3d400408, 0x72ff},
- {0x3d400494, 0x2100e07},
- {0x3d400498, 0x620096},
- {0x3d40049c, 0x1100e07},
- {0x3d4004a0, 0xc8012c},
- {0x3d402020, 0x21},
- {0x3d402024, 0x7d00},
- {0x3d402050, 0x20d040},
- {0x3d402064, 0xc001c},
- {0x3d4020dc, 0x840000},
- {0x3d4020e0, 0x310000},
- {0x3d4020e8, 0x66004d},
- {0x3d4020ec, 0x16004d},
- {0x3d402100, 0xa040305},
- {0x3d402104, 0x30407},
- {0x3d402108, 0x203060b},
- {0x3d40210c, 0x505000},
- {0x3d402110, 0x2040202},
- {0x3d402114, 0x2030202},
- {0x3d402118, 0x1010004},
- {0x3d40211c, 0x301},
- {0x3d402130, 0x20300},
- {0x3d402134, 0xa100002},
- {0x3d402138, 0x1d},
- {0x3d402144, 0x14000a},
- {0x3d402180, 0x640004},
- {0x3d402190, 0x3818200},
- {0x3d402194, 0x80303},
- {0x3d4021b4, 0x100},
- {0x3d403020, 0x21},
- {0x3d403024, 0x1f40},
- {0x3d403050, 0x20d040},
- {0x3d403064, 0x30007},
- {0x3d4030dc, 0x840000},
- {0x3d4030e0, 0x310000},
- {0x3d4030e8, 0x66004d},
- {0x3d4030ec, 0x16004d},
- {0x3d403100, 0xa010102},
- {0x3d403104, 0x30404},
- {0x3d403108, 0x203060b},
- {0x3d40310c, 0x505000},
- {0x3d403110, 0x2040202},
- {0x3d403114, 0x2030202},
- {0x3d403118, 0x1010004},
- {0x3d40311c, 0x301},
- {0x3d403130, 0x20300},
- {0x3d403134, 0xa100002},
- {0x3d403138, 0x8},
- {0x3d403144, 0x50003},
- {0x3d403180, 0x190004},
- {0x3d403190, 0x3818200},
- {0x3d403194, 0x80303},
- {0x3d4031b4, 0x100},
- {0x3d400028, 0x0},
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x63004d },
+ { 0x3d4000ec, 0x15004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d400028, 0x0 },
};
/* PHY Initialize Configuration */
struct dram_cfg_param ddr_ddrphy_cfg[] = {
- {0x100a0, 0x0},
- {0x100a1, 0x1},
- {0x100a2, 0x2},
- {0x100a3, 0x3},
- {0x100a4, 0x4},
- {0x100a5, 0x5},
- {0x100a6, 0x6},
- {0x100a7, 0x7},
- {0x110a0, 0x0},
- {0x110a1, 0x1},
- {0x110a2, 0x3},
- {0x110a3, 0x4},
- {0x110a4, 0x5},
- {0x110a5, 0x2},
- {0x110a6, 0x7},
- {0x110a7, 0x6},
- {0x120a0, 0x0},
- {0x120a1, 0x1},
- {0x120a2, 0x3},
- {0x120a3, 0x2},
- {0x120a4, 0x5},
- {0x120a5, 0x4},
- {0x120a6, 0x7},
- {0x120a7, 0x6},
- {0x130a0, 0x0},
- {0x130a1, 0x1},
- {0x130a2, 0x2},
- {0x130a3, 0x3},
- {0x130a4, 0x4},
- {0x130a5, 0x5},
- {0x130a6, 0x6},
- {0x130a7, 0x7},
- {0x1005f, 0x1ff},
- {0x1015f, 0x1ff},
- {0x1105f, 0x1ff},
- {0x1115f, 0x1ff},
- {0x1205f, 0x1ff},
- {0x1215f, 0x1ff},
- {0x1305f, 0x1ff},
- {0x1315f, 0x1ff},
- {0x11005f, 0x1ff},
- {0x11015f, 0x1ff},
- {0x11105f, 0x1ff},
- {0x11115f, 0x1ff},
- {0x11205f, 0x1ff},
- {0x11215f, 0x1ff},
- {0x11305f, 0x1ff},
- {0x11315f, 0x1ff},
- {0x21005f, 0x1ff},
- {0x21015f, 0x1ff},
- {0x21105f, 0x1ff},
- {0x21115f, 0x1ff},
- {0x21205f, 0x1ff},
- {0x21215f, 0x1ff},
- {0x21305f, 0x1ff},
- {0x21315f, 0x1ff},
- {0x55, 0x1ff},
- {0x1055, 0x1ff},
- {0x2055, 0x1ff},
- {0x3055, 0x1ff},
- {0x4055, 0x1ff},
- {0x5055, 0x1ff},
- {0x6055, 0x1ff},
- {0x7055, 0x1ff},
- {0x8055, 0x1ff},
- {0x9055, 0x1ff},
- {0x200c5, 0x19},
- {0x1200c5, 0x7},
- {0x2200c5, 0x7},
- {0x2002e, 0x2},
- {0x12002e, 0x2},
- {0x22002e, 0x2},
- {0x90204, 0x0},
- {0x190204, 0x0},
- {0x290204, 0x0},
- {0x20024, 0x1ab},
- {0x2003a, 0x0},
- {0x120024, 0x1ab},
- {0x2003a, 0x0},
- {0x220024, 0x1ab},
- {0x2003a, 0x0},
- {0x20056, 0x3},
- {0x120056, 0x3},
- {0x220056, 0x3},
- {0x1004d, 0xe00},
- {0x1014d, 0xe00},
- {0x1104d, 0xe00},
- {0x1114d, 0xe00},
- {0x1204d, 0xe00},
- {0x1214d, 0xe00},
- {0x1304d, 0xe00},
- {0x1314d, 0xe00},
- {0x11004d, 0xe00},
- {0x11014d, 0xe00},
- {0x11104d, 0xe00},
- {0x11114d, 0xe00},
- {0x11204d, 0xe00},
- {0x11214d, 0xe00},
- {0x11304d, 0xe00},
- {0x11314d, 0xe00},
- {0x21004d, 0xe00},
- {0x21014d, 0xe00},
- {0x21104d, 0xe00},
- {0x21114d, 0xe00},
- {0x21204d, 0xe00},
- {0x21214d, 0xe00},
- {0x21304d, 0xe00},
- {0x21314d, 0xe00},
- {0x10049, 0xeba},
- {0x10149, 0xeba},
- {0x11049, 0xeba},
- {0x11149, 0xeba},
- {0x12049, 0xeba},
- {0x12149, 0xeba},
- {0x13049, 0xeba},
- {0x13149, 0xeba},
- {0x110049, 0xeba},
- {0x110149, 0xeba},
- {0x111049, 0xeba},
- {0x111149, 0xeba},
- {0x112049, 0xeba},
- {0x112149, 0xeba},
- {0x113049, 0xeba},
- {0x113149, 0xeba},
- {0x210049, 0xeba},
- {0x210149, 0xeba},
- {0x211049, 0xeba},
- {0x211149, 0xeba},
- {0x212049, 0xeba},
- {0x212149, 0xeba},
- {0x213049, 0xeba},
- {0x213149, 0xeba},
- {0x43, 0x63},
- {0x1043, 0x63},
- {0x2043, 0x63},
- {0x3043, 0x63},
- {0x4043, 0x63},
- {0x5043, 0x63},
- {0x6043, 0x63},
- {0x7043, 0x63},
- {0x8043, 0x63},
- {0x9043, 0x63},
- {0x20018, 0x3},
- {0x20075, 0x4},
- {0x20050, 0x0},
- {0x20008, 0x2ee},
- {0x120008, 0x64},
- {0x220008, 0x19},
- {0x20088, 0x9},
- {0x200b2, 0xdc},
- {0x10043, 0x5a1},
- {0x10143, 0x5a1},
- {0x11043, 0x5a1},
- {0x11143, 0x5a1},
- {0x12043, 0x5a1},
- {0x12143, 0x5a1},
- {0x13043, 0x5a1},
- {0x13143, 0x5a1},
- {0x1200b2, 0xdc},
- {0x110043, 0x5a1},
- {0x110143, 0x5a1},
- {0x111043, 0x5a1},
- {0x111143, 0x5a1},
- {0x112043, 0x5a1},
- {0x112143, 0x5a1},
- {0x113043, 0x5a1},
- {0x113143, 0x5a1},
- {0x2200b2, 0xdc},
- {0x210043, 0x5a1},
- {0x210143, 0x5a1},
- {0x211043, 0x5a1},
- {0x211143, 0x5a1},
- {0x212043, 0x5a1},
- {0x212143, 0x5a1},
- {0x213043, 0x5a1},
- {0x213143, 0x5a1},
- {0x200fa, 0x1},
- {0x1200fa, 0x1},
- {0x2200fa, 0x1},
- {0x20019, 0x1},
- {0x120019, 0x1},
- {0x220019, 0x1},
- {0x200f0, 0x660},
- {0x200f1, 0x0},
- {0x200f2, 0x4444},
- {0x200f3, 0x8888},
- {0x200f4, 0x5665},
- {0x200f5, 0x0},
- {0x200f6, 0x0},
- {0x200f7, 0xf000},
- {0x20025, 0x0},
- {0x2002d, 0x0},
- {0x12002d, 0x0},
- {0x22002d, 0x0},
- {0x200c7, 0x21},
- {0x1200c7, 0x21},
- {0x2200c7, 0x21},
- {0x200ca, 0x24},
- {0x1200ca, 0x24},
- {0x2200ca, 0x24},
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x10049, 0x69a },
+ { 0x10149, 0x69a },
+ { 0x11049, 0x69a },
+ { 0x11149, 0x69a },
+ { 0x12049, 0x69a },
+ { 0x12149, 0x69a },
+ { 0x13049, 0x69a },
+ { 0x13149, 0x69a },
+ { 0x110049, 0x69a },
+ { 0x110149, 0x69a },
+ { 0x111049, 0x69a },
+ { 0x111149, 0x69a },
+ { 0x112049, 0x69a },
+ { 0x112149, 0x69a },
+ { 0x113049, 0x69a },
+ { 0x113149, 0x69a },
+ { 0x43, 0xe7 },
+ { 0x1043, 0xe7 },
+ { 0x2043, 0xe7 },
+ { 0x3043, 0xe7 },
+ { 0x4043, 0xe7 },
+ { 0x5043, 0xe7 },
+ { 0x6043, 0xe7 },
+ { 0x7043, 0xe7 },
+ { 0x8043, 0xe7 },
+ { 0x9043, 0xe7 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x200f0, 0x60 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5565 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
};
/* ddr phy trained csr */
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
- {0xd0000, 0x0},
- {0x54003, 0xbb8},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x131f},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x5400d, 0x100},
- {0x54012, 0x310},
- {0x54019, 0x2dd4},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x2dd4},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x3},
- {0x54032, 0xd400},
- {0x54033, 0x312d},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0xd400},
- {0x54039, 0x312d},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x3028 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d63 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d63 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6300 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6300 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1500 },
+ { 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
- {0xd0000, 0x0},
- {0x54002, 0x101},
- {0x54003, 0x190},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x121f},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x5400d, 0x100},
- {0x54012, 0x310},
- {0x54019, 0x84},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x84},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x3},
- {0x54032, 0x8400},
- {0x54033, 0x3100},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0x8400},
- {0x54039, 0x3100},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
-};
-
-/* P2 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg[] = {
- {0xd0000, 0x0},
- {0x54002, 0x102},
- {0x54003, 0x64},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x121f},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x5400d, 0x100},
- {0x54012, 0x310},
- {0x54019, 0x84},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x84},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x3},
- {0x54032, 0x8400},
- {0x54033, 0x3100},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0x8400},
- {0x54039, 0x3100},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x3028 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
- {0xd0000, 0x0},
- {0x54003, 0xbb8},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x61},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x5400f, 0x100},
- {0x54010, 0x1f7f},
- {0x54012, 0x310},
- {0x54019, 0x2dd4},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x2dd4},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x3},
- {0x54032, 0xd400},
- {0x54033, 0x312d},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0xd400},
- {0x54039, 0x312d},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x3028 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d63 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x15 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d63 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x15 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6300 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1500 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6300 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1500 },
{ 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
struct dram_cfg_param ddr_phy_pie[] = {
- {0xd0000, 0x0},
- {0x90000, 0x10},
- {0x90001, 0x400},
- {0x90002, 0x10e},
- {0x90003, 0x0},
- {0x90004, 0x0},
- {0x90005, 0x8},
- {0x90029, 0xb},
- {0x9002a, 0x480},
- {0x9002b, 0x109},
- {0x9002c, 0x8},
- {0x9002d, 0x448},
- {0x9002e, 0x139},
- {0x9002f, 0x8},
- {0x90030, 0x478},
- {0x90031, 0x109},
- {0x90032, 0x0},
- {0x90033, 0xe8},
- {0x90034, 0x109},
- {0x90035, 0x2},
- {0x90036, 0x10},
- {0x90037, 0x139},
- {0x90038, 0xf},
- {0x90039, 0x7c0},
- {0x9003a, 0x139},
- {0x9003b, 0x44},
- {0x9003c, 0x630},
- {0x9003d, 0x159},
- {0x9003e, 0x14f},
- {0x9003f, 0x630},
- {0x90040, 0x159},
- {0x90041, 0x47},
- {0x90042, 0x630},
- {0x90043, 0x149},
- {0x90044, 0x4f},
- {0x90045, 0x630},
- {0x90046, 0x179},
- {0x90047, 0x8},
- {0x90048, 0xe0},
- {0x90049, 0x109},
- {0x9004a, 0x0},
- {0x9004b, 0x7c8},
- {0x9004c, 0x109},
- {0x9004d, 0x0},
- {0x9004e, 0x1},
- {0x9004f, 0x8},
- {0x90050, 0x0},
- {0x90051, 0x45a},
- {0x90052, 0x9},
- {0x90053, 0x0},
- {0x90054, 0x448},
- {0x90055, 0x109},
- {0x90056, 0x40},
- {0x90057, 0x630},
- {0x90058, 0x179},
- {0x90059, 0x1},
- {0x9005a, 0x618},
- {0x9005b, 0x109},
- {0x9005c, 0x40c0},
- {0x9005d, 0x630},
- {0x9005e, 0x149},
- {0x9005f, 0x8},
- {0x90060, 0x4},
- {0x90061, 0x48},
- {0x90062, 0x4040},
- {0x90063, 0x630},
- {0x90064, 0x149},
- {0x90065, 0x0},
- {0x90066, 0x4},
- {0x90067, 0x48},
- {0x90068, 0x40},
- {0x90069, 0x630},
- {0x9006a, 0x149},
- {0x9006b, 0x10},
- {0x9006c, 0x4},
- {0x9006d, 0x18},
- {0x9006e, 0x0},
- {0x9006f, 0x4},
- {0x90070, 0x78},
- {0x90071, 0x549},
- {0x90072, 0x630},
- {0x90073, 0x159},
- {0x90074, 0xd49},
- {0x90075, 0x630},
- {0x90076, 0x159},
- {0x90077, 0x94a},
- {0x90078, 0x630},
- {0x90079, 0x159},
- {0x9007a, 0x441},
- {0x9007b, 0x630},
- {0x9007c, 0x149},
- {0x9007d, 0x42},
- {0x9007e, 0x630},
- {0x9007f, 0x149},
- {0x90080, 0x1},
- {0x90081, 0x630},
- {0x90082, 0x149},
- {0x90083, 0x0},
- {0x90084, 0xe0},
- {0x90085, 0x109},
- {0x90086, 0xa},
- {0x90087, 0x10},
- {0x90088, 0x109},
- {0x90089, 0x9},
- {0x9008a, 0x3c0},
- {0x9008b, 0x149},
- {0x9008c, 0x9},
- {0x9008d, 0x3c0},
- {0x9008e, 0x159},
- {0x9008f, 0x18},
- {0x90090, 0x10},
- {0x90091, 0x109},
- {0x90092, 0x0},
- {0x90093, 0x3c0},
- {0x90094, 0x109},
- {0x90095, 0x18},
- {0x90096, 0x4},
- {0x90097, 0x48},
- {0x90098, 0x18},
- {0x90099, 0x4},
- {0x9009a, 0x58},
- {0x9009b, 0xa},
- {0x9009c, 0x10},
- {0x9009d, 0x109},
- {0x9009e, 0x2},
- {0x9009f, 0x10},
- {0x900a0, 0x109},
- {0x900a1, 0x5},
- {0x900a2, 0x7c0},
- {0x900a3, 0x109},
- {0x900a4, 0x10},
- {0x900a5, 0x10},
- {0x900a6, 0x109},
- {0x40000, 0x811},
- {0x40020, 0x880},
- {0x40040, 0x0},
- {0x40060, 0x0},
- {0x40001, 0x4008},
- {0x40021, 0x83},
- {0x40041, 0x4f},
- {0x40061, 0x0},
- {0x40002, 0x4040},
- {0x40022, 0x83},
- {0x40042, 0x51},
- {0x40062, 0x0},
- {0x40003, 0x811},
- {0x40023, 0x880},
- {0x40043, 0x0},
- {0x40063, 0x0},
- {0x40004, 0x720},
- {0x40024, 0xf},
- {0x40044, 0x1740},
- {0x40064, 0x0},
- {0x40005, 0x16},
- {0x40025, 0x83},
- {0x40045, 0x4b},
- {0x40065, 0x0},
- {0x40006, 0x716},
- {0x40026, 0xf},
- {0x40046, 0x2001},
- {0x40066, 0x0},
- {0x40007, 0x716},
- {0x40027, 0xf},
- {0x40047, 0x2800},
- {0x40067, 0x0},
- {0x40008, 0x716},
- {0x40028, 0xf},
- {0x40048, 0xf00},
- {0x40068, 0x0},
- {0x40009, 0x720},
- {0x40029, 0xf},
- {0x40049, 0x1400},
- {0x40069, 0x0},
- {0x4000a, 0xe08},
- {0x4002a, 0xc15},
- {0x4004a, 0x0},
- {0x4006a, 0x0},
- {0x4000b, 0x623},
- {0x4002b, 0x15},
- {0x4004b, 0x0},
- {0x4006b, 0x0},
- {0x4000c, 0x4028},
- {0x4002c, 0x80},
- {0x4004c, 0x0},
- {0x4006c, 0x0},
- {0x4000d, 0xe08},
- {0x4002d, 0xc1a},
- {0x4004d, 0x0},
- {0x4006d, 0x0},
- {0x4000e, 0x623},
- {0x4002e, 0x1a},
- {0x4004e, 0x0},
- {0x4006e, 0x0},
- {0x4000f, 0x4040},
- {0x4002f, 0x80},
- {0x4004f, 0x0},
- {0x4006f, 0x0},
- {0x40010, 0x2604},
- {0x40030, 0x15},
- {0x40050, 0x0},
- {0x40070, 0x0},
- {0x40011, 0x708},
- {0x40031, 0x5},
- {0x40051, 0x0},
- {0x40071, 0x2002},
- {0x40012, 0x8},
- {0x40032, 0x80},
- {0x40052, 0x0},
- {0x40072, 0x0},
- {0x40013, 0x2604},
- {0x40033, 0x1a},
- {0x40053, 0x0},
- {0x40073, 0x0},
- {0x40014, 0x708},
- {0x40034, 0xa},
- {0x40054, 0x0},
- {0x40074, 0x2002},
- {0x40015, 0x4040},
- {0x40035, 0x80},
- {0x40055, 0x0},
- {0x40075, 0x0},
- {0x40016, 0x60a},
- {0x40036, 0x15},
- {0x40056, 0x1200},
- {0x40076, 0x0},
- {0x40017, 0x61a},
- {0x40037, 0x15},
- {0x40057, 0x1300},
- {0x40077, 0x0},
- {0x40018, 0x60a},
- {0x40038, 0x1a},
- {0x40058, 0x1200},
- {0x40078, 0x0},
- {0x40019, 0x642},
- {0x40039, 0x1a},
- {0x40059, 0x1300},
- {0x40079, 0x0},
- {0x4001a, 0x4808},
- {0x4003a, 0x880},
- {0x4005a, 0x0},
- {0x4007a, 0x0},
- {0x900a7, 0x0},
- {0x900a8, 0x790},
- {0x900a9, 0x11a},
- {0x900aa, 0x8},
- {0x900ab, 0x7aa},
- {0x900ac, 0x2a},
- {0x900ad, 0x10},
- {0x900ae, 0x7b2},
- {0x900af, 0x2a},
- {0x900b0, 0x0},
- {0x900b1, 0x7c8},
- {0x900b2, 0x109},
- {0x900b3, 0x10},
- {0x900b4, 0x2a8},
- {0x900b5, 0x129},
- {0x900b6, 0x8},
- {0x900b7, 0x370},
- {0x900b8, 0x129},
- {0x900b9, 0xa},
- {0x900ba, 0x3c8},
- {0x900bb, 0x1a9},
- {0x900bc, 0xc},
- {0x900bd, 0x408},
- {0x900be, 0x199},
- {0x900bf, 0x14},
- {0x900c0, 0x790},
- {0x900c1, 0x11a},
- {0x900c2, 0x8},
- {0x900c3, 0x4},
- {0x900c4, 0x18},
- {0x900c5, 0xe},
- {0x900c6, 0x408},
- {0x900c7, 0x199},
- {0x900c8, 0x8},
- {0x900c9, 0x8568},
- {0x900ca, 0x108},
- {0x900cb, 0x18},
- {0x900cc, 0x790},
- {0x900cd, 0x16a},
- {0x900ce, 0x8},
- {0x900cf, 0x1d8},
- {0x900d0, 0x169},
- {0x900d1, 0x10},
- {0x900d2, 0x8558},
- {0x900d3, 0x168},
- {0x900d4, 0x70},
- {0x900d5, 0x788},
- {0x900d6, 0x16a},
- {0x900d7, 0x1ff8},
- {0x900d8, 0x85a8},
- {0x900d9, 0x1e8},
- {0x900da, 0x50},
- {0x900db, 0x798},
- {0x900dc, 0x16a},
- {0x900dd, 0x60},
- {0x900de, 0x7a0},
- {0x900df, 0x16a},
- {0x900e0, 0x8},
- {0x900e1, 0x8310},
- {0x900e2, 0x168},
- {0x900e3, 0x8},
- {0x900e4, 0xa310},
- {0x900e5, 0x168},
- {0x900e6, 0xa},
- {0x900e7, 0x408},
- {0x900e8, 0x169},
- {0x900e9, 0x6e},
- {0x900ea, 0x0},
- {0x900eb, 0x68},
- {0x900ec, 0x0},
- {0x900ed, 0x408},
- {0x900ee, 0x169},
- {0x900ef, 0x0},
- {0x900f0, 0x8310},
- {0x900f1, 0x168},
- {0x900f2, 0x0},
- {0x900f3, 0xa310},
- {0x900f4, 0x168},
- {0x900f5, 0x1ff8},
- {0x900f6, 0x85a8},
- {0x900f7, 0x1e8},
- {0x900f8, 0x68},
- {0x900f9, 0x798},
- {0x900fa, 0x16a},
- {0x900fb, 0x78},
- {0x900fc, 0x7a0},
- {0x900fd, 0x16a},
- {0x900fe, 0x68},
- {0x900ff, 0x790},
- {0x90100, 0x16a},
- {0x90101, 0x8},
- {0x90102, 0x8b10},
- {0x90103, 0x168},
- {0x90104, 0x8},
- {0x90105, 0xab10},
- {0x90106, 0x168},
- {0x90107, 0xa},
- {0x90108, 0x408},
- {0x90109, 0x169},
- {0x9010a, 0x58},
- {0x9010b, 0x0},
- {0x9010c, 0x68},
- {0x9010d, 0x0},
- {0x9010e, 0x408},
- {0x9010f, 0x169},
- {0x90110, 0x0},
- {0x90111, 0x8b10},
- {0x90112, 0x168},
- {0x90113, 0x0},
- {0x90114, 0xab10},
- {0x90115, 0x168},
- {0x90116, 0x0},
- {0x90117, 0x1d8},
- {0x90118, 0x169},
- {0x90119, 0x80},
- {0x9011a, 0x790},
- {0x9011b, 0x16a},
- {0x9011c, 0x18},
- {0x9011d, 0x7aa},
- {0x9011e, 0x6a},
- {0x9011f, 0xa},
- {0x90120, 0x0},
- {0x90121, 0x1e9},
- {0x90122, 0x8},
- {0x90123, 0x8080},
- {0x90124, 0x108},
- {0x90125, 0xf},
- {0x90126, 0x408},
- {0x90127, 0x169},
- {0x90128, 0xc},
- {0x90129, 0x0},
- {0x9012a, 0x68},
- {0x9012b, 0x9},
- {0x9012c, 0x0},
- {0x9012d, 0x1a9},
- {0x9012e, 0x0},
- {0x9012f, 0x408},
- {0x90130, 0x169},
- {0x90131, 0x0},
- {0x90132, 0x8080},
- {0x90133, 0x108},
- {0x90134, 0x8},
- {0x90135, 0x7aa},
- {0x90136, 0x6a},
- {0x90137, 0x0},
- {0x90138, 0x8568},
- {0x90139, 0x108},
- {0x9013a, 0xb7},
- {0x9013b, 0x790},
- {0x9013c, 0x16a},
- {0x9013d, 0x1f},
- {0x9013e, 0x0},
- {0x9013f, 0x68},
- {0x90140, 0x8},
- {0x90141, 0x8558},
- {0x90142, 0x168},
- {0x90143, 0xf},
- {0x90144, 0x408},
- {0x90145, 0x169},
- {0x90146, 0xc},
- {0x90147, 0x0},
- {0x90148, 0x68},
- {0x90149, 0x0},
- {0x9014a, 0x408},
- {0x9014b, 0x169},
- {0x9014c, 0x0},
- {0x9014d, 0x8558},
- {0x9014e, 0x168},
- {0x9014f, 0x8},
- {0x90150, 0x3c8},
- {0x90151, 0x1a9},
- {0x90152, 0x3},
- {0x90153, 0x370},
- {0x90154, 0x129},
- {0x90155, 0x20},
- {0x90156, 0x2aa},
- {0x90157, 0x9},
- {0x90158, 0x0},
- {0x90159, 0x400},
- {0x9015a, 0x10e},
- {0x9015b, 0x8},
- {0x9015c, 0xe8},
- {0x9015d, 0x109},
- {0x9015e, 0x0},
- {0x9015f, 0x8140},
- {0x90160, 0x10c},
- {0x90161, 0x10},
- {0x90162, 0x8138},
- {0x90163, 0x10c},
- {0x90164, 0x8},
- {0x90165, 0x7c8},
- {0x90166, 0x101},
- {0x90167, 0x8},
- {0x90168, 0x0},
- {0x90169, 0x8},
- {0x9016a, 0x8},
- {0x9016b, 0x448},
- {0x9016c, 0x109},
- {0x9016d, 0xf},
- {0x9016e, 0x7c0},
- {0x9016f, 0x109},
- {0x90170, 0x0},
- {0x90171, 0xe8},
- {0x90172, 0x109},
- {0x90173, 0x47},
- {0x90174, 0x630},
- {0x90175, 0x109},
- {0x90176, 0x8},
- {0x90177, 0x618},
- {0x90178, 0x109},
- {0x90179, 0x8},
- {0x9017a, 0xe0},
- {0x9017b, 0x109},
- {0x9017c, 0x0},
- {0x9017d, 0x7c8},
- {0x9017e, 0x109},
- {0x9017f, 0x8},
- {0x90180, 0x8140},
- {0x90181, 0x10c},
- {0x90182, 0x0},
- {0x90183, 0x1},
- {0x90184, 0x8},
- {0x90185, 0x8},
- {0x90186, 0x4},
- {0x90187, 0x8},
- {0x90188, 0x8},
- {0x90189, 0x7c8},
- {0x9018a, 0x101},
- {0x90006, 0x0},
- {0x90007, 0x0},
- {0x90008, 0x8},
- {0x90009, 0x0},
- {0x9000a, 0x0},
- {0x9000b, 0x0},
- {0xd00e7, 0x400},
- {0x90017, 0x0},
- {0x9001f, 0x2a},
- {0x90026, 0x6a},
- {0x400d0, 0x0},
- {0x400d1, 0x101},
- {0x400d2, 0x105},
- {0x400d3, 0x107},
- {0x400d4, 0x10f},
- {0x400d5, 0x202},
- {0x400d6, 0x20a},
- {0x400d7, 0x20b},
- {0x2003a, 0x2},
- {0x2000b, 0x5d},
- {0x2000c, 0xbb},
- {0x2000d, 0x753},
- {0x2000e, 0x2c},
- {0x12000b, 0xc},
- {0x12000c, 0x19},
- {0x12000d, 0xfa},
- {0x12000e, 0x10},
- {0x22000b, 0x3},
- {0x22000c, 0x6},
- {0x22000d, 0x3e},
- {0x22000e, 0x10},
- {0x9000c, 0x0},
- {0x9000d, 0x173},
- {0x9000e, 0x60},
- {0x9000f, 0x6110},
- {0x90010, 0x2152},
- {0x90011, 0xdfbd},
- {0x90012, 0x60},
- {0x90013, 0x6152},
- {0x20010, 0x5a},
- {0x20011, 0x3},
- {0x120010, 0x5a},
- {0x120011, 0x3},
- {0x220010, 0x5a},
- {0x220011, 0x3},
- {0x40080, 0xe0},
- {0x40081, 0x12},
- {0x40082, 0xe0},
- {0x40083, 0x12},
- {0x40084, 0xe0},
- {0x40085, 0x12},
- {0x140080, 0xe0},
- {0x140081, 0x12},
- {0x140082, 0xe0},
- {0x140083, 0x12},
- {0x140084, 0xe0},
- {0x140085, 0x12},
- {0x240080, 0xe0},
- {0x240081, 0x12},
- {0x240082, 0xe0},
- {0x240083, 0x12},
- {0x240084, 0xe0},
- {0x240085, 0x12},
- {0x400fd, 0xf},
- {0x10011, 0x1},
- {0x10012, 0x1},
- {0x10013, 0x180},
- {0x10018, 0x1},
- {0x10002, 0x6209},
- {0x100b2, 0x1},
- {0x101b4, 0x1},
- {0x102b4, 0x1},
- {0x103b4, 0x1},
- {0x104b4, 0x1},
- {0x105b4, 0x1},
- {0x106b4, 0x1},
- {0x107b4, 0x1},
- {0x108b4, 0x1},
- {0x11011, 0x1},
- {0x11012, 0x1},
- {0x11013, 0x180},
- {0x11018, 0x1},
- {0x11002, 0x6209},
- {0x110b2, 0x1},
- {0x111b4, 0x1},
- {0x112b4, 0x1},
- {0x113b4, 0x1},
- {0x114b4, 0x1},
- {0x115b4, 0x1},
- {0x116b4, 0x1},
- {0x117b4, 0x1},
- {0x118b4, 0x1},
- {0x12011, 0x1},
- {0x12012, 0x1},
- {0x12013, 0x180},
- {0x12018, 0x1},
- {0x12002, 0x6209},
- {0x120b2, 0x1},
- {0x121b4, 0x1},
- {0x122b4, 0x1},
- {0x123b4, 0x1},
- {0x124b4, 0x1},
- {0x125b4, 0x1},
- {0x126b4, 0x1},
- {0x127b4, 0x1},
- {0x128b4, 0x1},
- {0x13011, 0x1},
- {0x13012, 0x1},
- {0x13013, 0x180},
- {0x13018, 0x1},
- {0x13002, 0x6209},
- {0x130b2, 0x1},
- {0x131b4, 0x1},
- {0x132b4, 0x1},
- {0x133b4, 0x1},
- {0x134b4, 0x1},
- {0x135b4, 0x1},
- {0x136b4, 0x1},
- {0x137b4, 0x1},
- {0x138b4, 0x1},
- {0x2003a, 0x2},
- {0xc0080, 0x2},
- {0xd0000, 0x1}
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
};
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
{
- /* P2 100mts 1D */
- .drate = 100,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
- },
- {
/* P0 3000mts 2D */
.drate = 3000,
.fw_type = FW_2D_IMAGE,
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 3000, 400, },
};
*/
#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
#include <efi.h>
#include <efi_loader.h>
+#include <env_internal.h>
#include <fdt_support.h>
#include <linux/errno.h>
#include <linux/kernel.h>
{
return 0;
}
+
+int board_late_init(void)
+{
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") ||
+ !fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-osm-s")) {
+ env_set("som_type", "osm-s");
+ env_set("touch_rst_gpio", "111");
+ } else {
+ env_set("som_type", "sl");
+ env_set("touch_rst_gpio", "87");
+ }
+
+ return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device boot_dev = get_boot_device();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ /*
+ * Make sure that the environment is loaded from
+ * the MMC if we are running from SD card or eMMC.
+ */
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC) &&
+ (boot_dev == SD1_BOOT || boot_dev == SD2_BOOT))
+ return ENVL_MMC;
+
+ if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+
+ return ENVL_NOWHERE;
+}
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+#endif
--- /dev/null
+kernel_addr_r=0x42000000
+fdt_addr_r=0x48000000
+fdtoverlay_addr_r=0x49000000
+ramdisk_addr_r=0x48080000
+scriptaddr=0x40000000
+pxefile_addr_r=0x40100000
+dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000
enum {
BOARD_TYPE_KTN_N801X,
- BOARD_TYPE_KTN_N801X_LVDS,
+ BOARD_TYPE_KTN_N802X,
BOARD_TYPE_MAX
};
-#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
-
static iomux_v3_cfg_t const i2c1_pads[] = {
IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
};
-static iomux_v3_cfg_t const i2c2_pads[] = {
- IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
- IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
-};
-
-static iomux_v3_cfg_t const touch_gpio[] = {
- IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
-};
-
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
dram_timing.ddrc_cfg[2].val = 0xa1080020;
dram_timing.ddrc_cfg[37].val = 0x1f;
- dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
- dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
- dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
- dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
+ dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x110;
+ dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x1;
+ dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x110;
+ dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x1;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
- dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
- dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
if (!ddr_init(&dram_timing)) {
if (check_ram_available(SZ_2G))
size = 1;
}
- printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
+ gd->ram_size = size;
writel(size, M4_BOOTROM_BASE_ADDR);
}
-static void touch_reset(void)
-{
- /*
- * Toggle the reset of the touch panel.
- */
- imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
-
- gpio_request(TOUCH_RESET_GPIO, "touch_reset");
- gpio_direction_output(TOUCH_RESET_GPIO, 0);
- mdelay(20);
- gpio_direction_output(TOUCH_RESET_GPIO, 1);
- mdelay(20);
-}
-
-static int i2c_detect(u8 bus, u16 addr)
-{
- struct udevice *udev;
- int ret;
-
- /*
- * Try to probe the touch controller to check if an LVDS panel is
- * connected.
- */
- ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
- if (ret == 0)
- return 0;
-
- return 1;
-}
-
int do_board_detect(void)
{
- bool lvds = false;
+ struct udevice *udev;
/*
- * Check the I2C touch controller to detect a LVDS panel.
+ * Check for the RTC on the OSM module.
*/
- imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
- touch_reset();
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
- if (i2c_detect(1, 0x5d) == 0) {
- printf("Touch controller detected, assuming LVDS panel...\n");
- lvds = true;
+ if (i2c_get_chip_for_busnum(0, 0x52, 0, &udev) == 0) {
+ gd->board_type = BOARD_TYPE_KTN_N802X;
+ printf("Kontron OSM-S i.MX8MM (N802X) module, %u GB RAM detected\n",
+ (unsigned int)gd->ram_size);
+ } else {
+ gd->board_type = BOARD_TYPE_KTN_N801X;
+ printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n",
+ (unsigned int)gd->ram_size);
}
/*
*/
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
- if (i2c_detect(0, 0x58) == 0) {
+ if (i2c_get_chip_for_busnum(0, 0x58, 0, &udev) == 0) {
printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
- printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
+ printf("### THIS HW IS NOT SUPPORTED AND BOOTING WILL PROBABLY FAIL ###\n");
printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
}
- if (lvds)
- gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
- else
- gd->board_type = BOARD_TYPE_KTN_N801X;
-
return 0;
}
int board_fit_config_name_match(const char *name)
{
- if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
- !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
+ if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
+ (!strcmp(name, "imx8mm-kontron-n801x-s") ||
+ !strcmp(name, "imx8mm-kontron-bl")))
return 0;
- if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
- !strncmp(name, "imx8mm-kontron-n801x-s", 22))
+ if (gd->board_type == BOARD_TYPE_KTN_N802X && is_imx8mm() &&
+ (!strcmp(name, "imx8mm-kontron-n802x-s") ||
+ !strcmp(name, "imx8mm-kontron-bl-osm-s")))
return 0;
return -1;
struct udevice *dev;
int ret;
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
- }
+ arch_misc_init();
puts("Normal Boot\n");
board_init_r(NULL, 0);
}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- u32 bootdev = spl_boot_device();
-
- /*
- * The default boot fuse settings use the SD card (MMC2) as primary
- * boot device, but allow SPI NOR as a fallback boot device.
- * We can't detect the fallback case and spl_boot_device() will return
- * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
- * Therefore we try to load U-Boot proper vom SPI NOR after loading
- * from MMC has failed.
- */
- spl_boot_list[0] = bootdev;
-
- switch (bootdev) {
- case BOOT_DEVICE_MMC1:
- case BOOT_DEVICE_MMC2:
- spl_boot_list[1] = BOOT_DEVICE_SPI;
- break;
- }
-}
void board_early_init(void)
{
- init_uart_clk(1);
+ init_uart_clk(0);
}
ddr_init(&dram_timing);
}
-void spl_board_init(void)
-{
- /* Serial download mode */
- if (is_usb_boot()) {
- puts("Back to ROM, SDP\n");
- restore_boot_params();
- }
- puts("Normal Boot\n");
-}
-
int board_fit_config_name_match(const char *name)
{
return 0;
TBS2910 BOARD
M: Soeren Moch <smoch@web.de>
S: Maintained
-F: arch/arm/dts/imx6q-tbs2910.dts
+F: arch/arm/dts/imx6q-tbs2910*
F: board/tbs/tbs2910/
F: configs/tbs2910_defconfig
F: doc/board/tbs/
void spl_board_init(void)
{
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
- }
-
- /* Serial download mode */
- if (is_usb_boot()) {
- puts("Back to ROM, SDP\n");
- restore_boot_params();
- }
- puts("Normal Boot\n");
+ arch_misc_init();
}
#ifdef CONFIG_SPL_LOAD_FIT
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
- return 0;
+ return ft_common_board_setup(blob, bd);
}
#endif
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/ddr.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
#include <power/pmic.h>
#include <power/pca9450.h>
void spl_board_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize caam_jr: %d\n", ret);
+ }
+
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
return 0;
}
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
- return 0;
+ return ft_common_board_setup(blob, bd);
}
#endif
help
Acquire a network IP address using the link-local protocol
+config CMD_NCSI
+ bool "ncsi"
+ depends on PHY_NCSI
+ help
+ Manually configure the attached NIC via NC-SI.
+ Normally this happens automatically before other network
+ operations.
+
endif
config CMD_ETHSW
#include <part.h>
#include <malloc.h>
#include <memalign.h>
+#include <linux/err.h>
enum bcb_cmd {
BCB_CMD_LOAD,
goto err_read_fail;
}
+ /*
+ * always select the USER mmc hwpart in case another
+ * blk operation selected a different hwpart
+ */
+ ret = blk_dselect_hwpart(desc, 0);
+ if (IS_ERR_VALUE(ret)) {
+ ret = -ENODEV;
+ goto err_read_fail;
+ }
+
part = simple_strtoul(partp, &endp, 0);
if (*endp == '\0') {
ret = part_get_info(desc, part, &info);
#include <net.h>
#include <net/udp.h>
#include <net/sntp.h>
+#include <net/ncsi.h>
static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []);
"list - list available devices\n"
);
#endif // CONFIG_DM_ETH
+
+#if defined(CONFIG_CMD_NCSI)
+static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (!phy_interface_is_ncsi() || !ncsi_active()) {
+ printf("Device not configured for NC-SI\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (net_loop(NCSI) < 0)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ ncsi, 1, 1, do_ncsi,
+ "Configure attached NIC via NC-SI",
+ ""
+);
+#endif /* CONFIG_CMD_NCSI */
qfw_read_entry(qfw_dev, FW_CFG_KERNEL_SIZE, 4, &kernel_size);
if (kernel_size == 0) {
- printf("warning: no kernel available\n");
- return -1;
+ printf("fatal: no kernel available\n");
+ return CMD_RET_FAILURE;
}
data_addr = load_addr;
qfw_read_entry(qfw_dev, FW_CFG_KERNEL_DATA,
le32_to_cpu(kernel_size), data_addr);
data_addr += le32_to_cpu(kernel_size);
+ env_set_hex("filesize", le32_to_cpu(kernel_size));
data_addr = initrd_addr;
qfw_read_entry(qfw_dev, FW_CFG_INITRD_SIZE, 4, &initrd_size);
qfw_read_entry(qfw_dev, FW_CFG_INITRD_DATA,
le32_to_cpu(initrd_size), data_addr);
data_addr += le32_to_cpu(initrd_size);
+ env_set_hex("filesize", le32_to_cpu(initrd_size));
}
qfw_read_entry(qfw_dev, FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
{
struct udevice *dev;
char status[256];
+ bool status_printed = false;
int ret;
- ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
- if (ret) {
- debug("%s: No sysreset device found (error: %d)\n",
- __func__, ret);
- /* Not all boards have sysreset drivers available during early
- * boot, so don't fail if one can't be found.
- */
- return 0;
- }
+ /* Not all boards have sysreset drivers available during early
+ * boot, so don't fail if one can't be found.
+ */
+ for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev;
+ ret = uclass_next_device_check(&dev)) {
+ if (ret) {
+ debug("%s: %s sysreset device (error: %d)\n",
+ __func__, dev->name, ret);
+ continue;
+ }
- if (!sysreset_get_status(dev, status, sizeof(status)))
- printf("%s", status);
+ if (!sysreset_get_status(dev, status, sizeof(status))) {
+ printf("%s%s", status_printed ? " " : "", status);
+ status_printed = true;
+ }
+ }
+ if (status_printed)
+ printf("\n");
return 0;
}
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SYS_LOAD_ADDR=0x14200000
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc-eval-v3"
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+CONFIG_SYS_LOAD_ADDR=0x84200000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-eval-v3"
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+CONFIG_SYS_LOAD_ADDR=0x84200000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_SYS_LOAD_ADDR=0x14200000
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
+CONFIG_SYS_LOAD_ADDR=0x84200000
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=544
-# CONFIG_CMD_BOOTD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
+CONFIG_SYS_LOAD_ADDR=0x84200000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x8c000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=544
-# CONFIG_CMD_BOOTD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
CONFIG_FTGMAC100=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
CONFIG_CMD_EXT4=y
CONFIG_DOS_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
CONFIG_DM_MDIO=y
CONFIG_FTGMAC100=y
CONFIG_ASPEED_MDIO=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+# CONFIG_USB_STORAGE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Menlo"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_SPL_PHY=y
+CONFIG_SPL_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+# CONFIG_USB_STORAGE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_OF_LIST="imx8mn-venice imx8mn-venice-gw7902"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-icore-mx8mp-edimm2.2.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x98fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x960000
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_SYS_BOOTM_LEN=0x2000000
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_I2C is not set
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_BTRFS=y
CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_MX6UL=y
CONFIG_TARGET_KONTRON_MX6UL=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s"
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-bl"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s"
+CONFIG_OF_LIST="imx6ul-kontron-bl imx6ull-kontron-bl"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_BUS=2
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth0"
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x1f0000
+CONFIG_ENV_OFFSET=0x1E0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-bl"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_KONTRON_MX8MM=y
CONFIG_SPL_MMC=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x1F0000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOARD_TYPES=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_LZMADEC is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
+CONFIG_OF_LIST="imx8mm-kontron-bl imx8mm-kontron-bl-osm-s"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_DM_RTC=y
+CONFIG_RTC_RV3028=y
CONFIG_RTC_RV8803=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK=0x920000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc rescan; if run bootcmd_up1; then run bootcmd_up2; else run bootcmd_mmc || run distro_bootcmd; fi"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
+CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start"
CONFIG_DEFAULT_FDT_FILE="imx6q-tbs2910.dtb"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_HUSH_PARSER=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_RX_BUFFER=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
CONFIG_SPL=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_LOAD_ADDR=0x48280000
+CONFIG_SYS_LOAD_ADDR=0x48200000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_BOOTCOUNT_ENV=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_SYS_LOAD_ADDR=0x48280000
+CONFIG_SYS_LOAD_ADDR=0x48200000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_CRC32 is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
+CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_FSL_CAAM=y
.. SPDX-License-Identifier: GPL-2.0+
-Kontron Electronics SL i.MX8MM SoM
-==================================
+Kontron Electronics i.MX8MM SoMs and Boards
+===========================================
-The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
+The SL i.MX8MM and OSM-S i.MX8MM by Kontron Electronics GmbH are SoM modules
with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
-The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
-HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
+The matching evaluation boards (Board-Line, BL) have two Ethernet ports,
+USB 2.0, HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
+
+The OSM-S i.MX8MM is compliant to the Open Standard Module (OSM) 1.0
+specification, size S (https://sget.org/standards/osm).
Quick Start
-----------
static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
-#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
"sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+#endif
static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+#if CONFIG_IS_ENABLED(NXP_FSPI)
static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
+#endif
static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+#if CONFIG_IS_ENABLED(DM_SPI)
static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+#endif
static int imx8mm_clk_probe(struct udevice *dev)
{
clk_dm(IMX8MM_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
- clk_dm(IMX8MM_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
- base + 0x8880));
clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
imx8m_clk_composite_critical("nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
- clk_dm(IMX8MM_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
- clk_dm(IMX8MM_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
- clk_dm(IMX8MM_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
- clk_dm(IMX8MM_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_WDOG,
imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
base + 0xbc80));
- clk_dm(IMX8MM_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
clk_dm(IMX8MM_CLK_USB_CORE_REF,
imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
clk_dm(IMX8MM_CLK_USB_PHY_REF,
imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
- clk_dm(IMX8MM_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
- clk_dm(IMX8MM_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
- clk_dm(IMX8MM_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
-
- clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
- imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
- clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
- imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
- clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
- imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
- clk_dm(IMX8MM_CLK_PWM1_ROOT,
- imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
- clk_dm(IMX8MM_CLK_PWM2_ROOT,
- imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
- clk_dm(IMX8MM_CLK_PWM3_ROOT,
- imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
- clk_dm(IMX8MM_CLK_PWM4_ROOT,
- imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
- clk_dm(IMX8MM_CLK_QSPI_ROOT,
- imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
+ clk_dm(IMX8MM_CLK_ENET_AXI,
+ imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+ base + 0x8880));
clk_dm(IMX8MM_CLK_ENET_REF,
imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MM_CLK_ENET1_ROOT,
imx_clk_gate4("enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+#endif
+
+#if CONFIG_IS_ENABLED(DM_SPI)
+ clk_dm(IMX8MM_CLK_ECSPI1,
+ imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MM_CLK_ECSPI2,
+ imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MM_CLK_ECSPI3,
+ imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+
+ clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
+ imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
+ imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
+ imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+#endif
+
+#if CONFIG_IS_ENABLED(NXP_FSPI)
+ clk_dm(IMX8MM_CLK_QSPI,
+ imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MM_CLK_QSPI_ROOT,
+ imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
return 0;
#include <config.h>
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
#include <log.h>
#include <asm/types.h>
inline_cnstr_jobdesc_pkha_rsaexp(desc, &pkin, out, sig_len);
+ flush_dcache_range((ulong)sig, (ulong)sig + sig_len);
+ flush_dcache_range((ulong)prop->modulus, (ulong)(prop->modulus) + keylen);
+ flush_dcache_range((ulong)prop->public_exponent,
+ (ulong)(prop->public_exponent) + prop->exp_len);
+ flush_dcache_range((ulong)desc, (ulong)desc + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
+ flush_dcache_range((ulong)out, (ulong)out + sig_len);
+
ret = run_descriptor_jr(desc);
if (ret) {
debug("%s: RSA failed to verify: %d\n", __func__, ret);
return -EFAULT;
}
+ invalidate_dcache_range((ulong)out, (ulong)out + sig_len);
+
return 0;
}
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
- tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+ while (tmp) { //try to find a significant byte in the word
+ if (tmp & 0xff) {
+ tmp &= 0xff;
+ break;
+ }
+ tmp >>= 8;
+ }
return tmp;
}
help
Support for GPIOs on Faraday Technology's FTGPIO010 controller.
+config ADP5585_GPIO
+ bool "ADP5585 GPIO driver"
+ depends on DM_GPIO && DM_I2C
+ help
+ Support ADP5585 GPIO expander.
+
endif
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
+obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * ADP5585 I/O Expander Controller
+ *
+ * Author: Alice Guo <alice.guo@nxp.com>
+ */
+
+#include <asm/gpio.h>
+#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <i2c.h>
+
+#define ADP5585_ID 0x00
+#define ADP5585_INT_STATUS 0x01
+#define ADP5585_STATUS 0x02
+#define ADP5585_FIFO_1 0x03
+#define ADP5585_FIFO_2 0x04
+#define ADP5585_FIFO_3 0x05
+#define ADP5585_FIFO_4 0x06
+#define ADP5585_FIFO_5 0x07
+#define ADP5585_FIFO_6 0x08
+#define ADP5585_FIFO_7 0x09
+#define ADP5585_FIFO_8 0x0A
+#define ADP5585_FIFO_9 0x0B
+#define ADP5585_FIFO_10 0x0C
+#define ADP5585_FIFO_11 0x0D
+#define ADP5585_FIFO_12 0x0E
+#define ADP5585_FIFO_13 0x0F
+#define ADP5585_FIFO_14 0x10
+#define ADP5585_FIFO_15 0x11
+#define ADP5585_FIFO_16 0x12
+#define ADP5585_GPI_INT_STAT_A 0x13
+#define ADP5585_GPI_INT_STAT_B 0x14
+#define ADP5585_GPI_STATUS_A 0x15
+#define ADP5585_GPI_STATUS_B 0x16
+#define ADP5585_RPULL_CONFIG_A 0x17
+#define ADP5585_RPULL_CONFIG_B 0x18
+#define ADP5585_RPULL_CONFIG_C 0x19
+#define ADP5585_RPULL_CONFIG_D 0x1A
+#define ADP5585_GPI_INT_LEVEL_A 0x1B
+#define ADP5585_GPI_INT_LEVEL_B 0x1C
+#define ADP5585_GPI_EVENT_EN_A 0x1D
+#define ADP5585_GPI_EVENT_EN_B 0x1E
+#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
+#define ADP5585_GPI_INTERRUPT_EN_B 0x20
+#define ADP5585_DEBOUNCE_DIS_A 0x21
+#define ADP5585_DEBOUNCE_DIS_B 0x22
+#define ADP5585_GPO_DATA_OUT_A 0x23
+#define ADP5585_GPO_DATA_OUT_B 0x24
+#define ADP5585_GPO_OUT_MODE_A 0x25
+#define ADP5585_GPO_OUT_MODE_B 0x26
+#define ADP5585_GPIO_DIRECTION_A 0x27
+#define ADP5585_GPIO_DIRECTION_B 0x28
+#define ADP5585_RESET1_EVENT_A 0x29
+#define ADP5585_RESET1_EVENT_B 0x2A
+#define ADP5585_RESET1_EVENT_C 0x2B
+#define ADP5585_RESET2_EVENT_A 0x2C
+#define ADP5585_RESET2_EVENT_B 0x2D
+#define ADP5585_RESET_CFG 0x2E
+#define ADP5585_PWM_OFFT_LOW 0x2F
+#define ADP5585_PWM_OFFT_HIGH 0x30
+#define ADP5585_PWM_ONT_LOW 0x31
+#define ADP5585_PWM_ONT_HIGH 0x32
+#define ADP5585_PWM_CFG 0x33
+#define ADP5585_LOGIC_CFG 0x34
+#define ADP5585_LOGIC_FF_CFG 0x35
+#define ADP5585_LOGIC_INT_EVENT_EN 0x36
+#define ADP5585_POLL_PTIME_CFG 0x37
+#define ADP5585_PIN_CONFIG_A 0x38
+#define ADP5585_PIN_CONFIG_B 0x39
+#define ADP5585_PIN_CONFIG_D 0x3A
+#define ADP5585_GENERAL_CFG 0x3B
+#define ADP5585_INT_EN 0x3C
+
+#define ADP5585_MAXGPIO 10
+#define ADP5585_BANK(offs) ((offs) > 4)
+#define ADP5585_BIT(offs) ((offs) > 4 ? \
+ 1u << ((offs) - 5) : 1u << (offs))
+
+struct adp5585_plat {
+ fdt_addr_t addr;
+ u8 id;
+ u8 dat_out[2];
+ u8 dir[2];
+};
+
+static int adp5585_direction_input(struct udevice *dev, unsigned int offset)
+{
+ int ret;
+ unsigned int bank;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+
+ plat->dir[bank] &= ~ADP5585_BIT(offset);
+ ret = dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ int ret;
+ unsigned int bank, bit;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+
+ plat->dir[bank] |= bit;
+
+ if (value)
+ plat->dat_out[bank] |= bit;
+ else
+ plat->dat_out[bank] &= ~bit;
+
+ ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+ ret |= dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct adp5585_plat *plat = dev_get_plat(dev);
+ unsigned int bank = ADP5585_BANK(offset);
+ unsigned int bit = ADP5585_BIT(offset);
+ u8 val;
+
+ if (plat->dir[bank] & bit)
+ val = plat->dat_out[bank];
+ else
+ dm_i2c_read(dev, ADP5585_GPI_STATUS_A + bank, &val, 1);
+
+ return !!(val & bit);
+}
+
+static int adp5585_set_value(struct udevice *dev, unsigned int offset, int value)
+{
+ int ret;
+ unsigned int bank, bit;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+
+ if (value)
+ plat->dat_out[bank] |= bit;
+ else
+ plat->dat_out[bank] &= ~bit;
+
+ ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+
+ return ret;
+}
+
+static int adp5585_get_function(struct udevice *dev, unsigned int offset)
+{
+ unsigned int bank, bit, dir;
+ struct adp5585_plat *plat = dev_get_plat(dev);
+
+ bank = ADP5585_BANK(offset);
+ bit = ADP5585_BIT(offset);
+ dir = plat->dir[bank] & bit;
+
+ if (!dir)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static int adp5585_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops adp5585_ops = {
+ .direction_input = adp5585_direction_input,
+ .direction_output = adp5585_direction_output,
+ .get_value = adp5585_get_value,
+ .set_value = adp5585_set_value,
+ .get_function = adp5585_get_function,
+ .xlate = adp5585_xlate,
+};
+
+static int adp5585_probe(struct udevice *dev)
+{
+ struct adp5585_plat *plat = dev_get_plat(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ if (!plat)
+ return 0;
+
+ plat->addr = dev_read_addr(dev);
+ if (plat->addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev, ADP5585_ID, &plat->id, 1);
+ if (ret < 0)
+ return ret;
+
+ uc_priv->gpio_count = ADP5585_MAXGPIO;
+ uc_priv->bank_name = "adp5585-gpio";
+
+ for (int i = 0; i < 2; i++) {
+ ret = dm_i2c_read(dev, ADP5585_GPO_DATA_OUT_A + i, &plat->dat_out[i], 1);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_read(dev, ADP5585_GPIO_DIRECTION_A + i, &plat->dir[i], 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id adp5585_ids[] = {
+ { .compatible = "adp5585" },
+ { }
+};
+
+U_BOOT_DRIVER(adp5585) = {
+ .name = "adp5585",
+ .id = UCLASS_GPIO,
+ .of_match = adp5585_ids,
+ .probe = adp5585_probe,
+ .ops = &adp5585_ops,
+ .plat_auto = sizeof(struct adp5585_plat),
+};
If unsure, say N.
config MMC_SDHCI_F_SDH30
- bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30"
depends on BLK && DM_MMC
depends on MMC_SDHCI
help
This selects the Secure Digital Host Controller Interface (SDHCI)
- Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ Needed by some Fujitsu/Socionext SoC for MMC / SD / SDIO support.
If you have a controller with this interface, say Y or M here.
If unsure, say N.
if (data->flags == MMC_DATA_READ &&
(mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
+ mask & (DWMCI_INTMSK_RXDR |
+ DWMCI_INTMSK_DTO));
while (size) {
ret = dwmci_fifo_ready(host,
DWMCI_FIFO_EMPTY,
#include <malloc.h>
#include <sdhci.h>
+#define F_SDH30_ESD_CONTROL 0x124
+#define F_SDH30_CMD_DAT_DELAY BIT(9)
+
+#define F_SDH30_TEST 0x158
+#define F_SDH30_FORCE_CARD_INSERT BIT(6)
+
+struct f_sdh30_data {
+ void (*init)(struct udevice *dev);
+ u32 quirks;
+};
+
struct f_sdh30_plat {
struct mmc_config cfg;
struct mmc mmc;
+
+ bool enable_cmd_dat_delay;
+ const struct f_sdh30_data *data;
};
DECLARE_GLOBAL_DATA_PTR;
+static void f_sdh30_e51_init(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ u32 val;
+
+ val = sdhci_readl(host, F_SDH30_ESD_CONTROL);
+ if (plat->enable_cmd_dat_delay)
+ val |= F_SDH30_CMD_DAT_DELAY;
+ else
+ val &= ~F_SDH30_CMD_DAT_DELAY;
+ sdhci_writel(host, val, F_SDH30_ESD_CONTROL);
+
+ val = sdhci_readl(host, F_SDH30_TEST);
+ if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
+ val |= F_SDH30_FORCE_CARD_INSERT;
+ else
+ val &= ~F_SDH30_FORCE_CARD_INSERT;
+ sdhci_writel(host, val, F_SDH30_TEST);
+}
+
static int f_sdh30_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
+ plat->data = (const struct f_sdh30_data *)dev_get_driver_data(dev);
+
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
host->mmc->dev = dev;
host->mmc->priv = host;
+ if (plat->data && plat->data->quirks)
+ host->quirks = plat->data->quirks;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000);
if (ret)
return ret;
mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
- return sdhci_probe(dev);
+ ret = sdhci_probe(dev);
+ if (ret)
+ return ret;
+
+ if (plat->data && plat->data->init)
+ plat->data->init(dev);
+
+ return 0;
}
static int f_sdh30_of_to_plat(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
host->name = strdup(dev->name);
host->ioaddr = dev_read_addr_ptr(dev);
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
host->index = dev_read_u32_default(dev, "index", 0);
+ plat->enable_cmd_dat_delay =
+ dev_read_bool(dev, "socionext,enable-cmd-dat-delay");
+
return 0;
}
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct f_sdh30_data f_sdh30_e51_data = {
+ .init = f_sdh30_e51_init,
+ .quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_SUPPORT_SINGLE,
+};
+
static const struct udevice_id f_sdh30_mmc_ids[] = {
- { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ {
+ .compatible = "fujitsu,mb86s70-sdhci-3.0",
+ },
+ {
+ .compatible = "socionext,f-sdh30-e51-mmc",
+ .data = (ulong)&f_sdh30_e51_data,
+ },
{ }
};
* work as expected.
*/
- init_clk_usdhc(dev_seq(dev));
-
#if CONFIG_IS_ENABLED(CLK)
/* Assigned clock already set clock */
ret = clk_get_by_name(dev, "per", &priv->per_clk);
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
#else
+ init_clk_usdhc(dev_seq(dev));
+
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
#include <syscon.h>
#include <linux/err.h>
-#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
}
m = mmc_get_mmc_dev(dev);
- m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
-
if (!m)
return 0;
+
+ /* Initialising user set speed mode */
+ m->user_speed_mode = MMC_MODES_END;
+
if (m->preinit)
mmc_start_init(m);
unsigned int stat = 0;
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
- u32 mask, flags, mode;
+ u32 mask, flags, mode = 0;
unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
ulong start = get_timer(0);
/* Set Transfer mode regarding to data flag */
if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
- mode = SDHCI_TRNS_BLK_CNT_EN;
+
+ if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
+ mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
if (data->blocks > 1)
- mode |= SDHCI_TRNS_MULTI;
+ mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/iopoll.h>
+#include <power/regulator.h>
#include <watchdog.h>
struct stm32_sdmmc2_plat {
struct gpio_desc cd_gpio;
u32 clk_reg_msk;
u32 pwr_reg_msk;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ bool vqmmc_enabled;
+#endif
};
struct stm32_sdmmc2_ctx {
plat->base + SDMMC_POWER);
/* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (plat->mmc.vqmmc_supply && !plat->vqmmc_enabled) {
+ if (regulator_set_enable_if_allowed(plat->mmc.vqmmc_supply, true))
+ dev_dbg(plat->mmc.dev, "failed to enable vqmmc-supply\n");
+ else
+ plat->vqmmc_enabled = true;
+ }
+#endif
}
#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
- if (desired && ((sys_clock > desired) ||
+ if (desired && (sys_clock > desired || mmc->ddr_mode ||
IS_RISING_EDGE(plat->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
+ if (mmc->ddr_mode)
+ clk |= SDMMC_CLKCR_DDR;
+
if (mmc->bus_width == 4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mmc->bus_width == 8)
if (ret)
return ret;
+ cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES);
+
ret = clk_get_by_index(dev, 0, &plat->clk);
if (ret)
return ret;
struct phy_device *phydev = priv->phydev;
u32 maccr;
- if (!phydev->link) {
+ if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
dev_err(phydev->dev, "No link\n");
return -EREMOTEIO;
}
if (!phydev)
return -ENODEV;
- phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+ phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
if (ret)
writel(0, &ftgmac100->maccr);
- phy_shutdown(priv->phydev);
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+ phy_shutdown(priv->phydev);
}
static int ftgmac100_start(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
+ if (dev_read_bool(dev, "use-ncsi"))
+ priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
+
#ifdef CONFIG_PHY_ADDR
priv->phy_addr = CONFIG_PHY_ADDR;
#endif
* If DM MDIO is enabled, the MDIO bus will be initialized later in
* dm_eth_phy_connect
*/
- if (!IS_ENABLED(CONFIG_DM_MDIO)) {
+ if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
+ !IS_ENABLED(CONFIG_DM_MDIO)) {
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
#include <log.h>
#include <malloc.h>
#include <phy.h>
+#include <net.h>
#include <net/ncsi.h>
#include <net/ncsi-pkt.h>
#include <asm/unaligned.h>
#endif
#ifdef CONFIG_PHY_NCSI
- if (!phydev)
+ if (!phydev && interface == PHY_INTERFACE_MODE_NCSI)
phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
#endif
return 0;
}
+
+bool phy_interface_is_ncsi(void)
+{
+ struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
+
+ return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+}
* @param start - starting block number
* @param blkcnt - number of blocks to read
* @param blksz - size in bytes of each block
- * @param buf - buffer to contain cached data
+ * @param buffer - buffer to contain cached data
*
* Return: - 1 if block returned from cache, 0 otherwise.
*/
* @param start - starting block number
* @param blkcnt - number of blocks available
* @param blksz - size in bytes of each block
- * @param buf - buffer containing data to cache
+ * @param buffer - buffer containing data to cache
*
*/
void blkcache_fill(int iftype, int dev,
* The MMC standard provides for two boot partitions (numbered 1 and 2),
* rpmb (3), and up to 4 addition general-purpose partitions (4-7).
*
- * @desc: Block device to update
+ * @dev: Block device to update
* @hwpart: Hardware partition number to select. 0 means the raw
* device, 1 is the first partition, 2 is the second, etc.
* @return 0 if OK, -ve on error
*
* @uclass_id: Block device type
* @devnum: Device number
+ * @start: Start block number to read (0=first)
* @blkcnt: Number of blocks to read
* @buffer: Address to write data to
* Return: number of blocks read, or -ve error number on error
*
* @uclass_id: Block device type
* @devnum: Device number
+ * @start: Start block number to write (0=first)
* @blkcnt: Number of blocks to write
* @buffer: Address to read data from
* Return: number of blocks written, or -ve error number on error
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
- "fdt_addr_r=0x12100000\0" \
- "kernel_addr_r=0x11000000\0" \
- "pxefile_addr_r=0x17100000\0" \
- "ramdisk_addr_r=0x12200000\0" \
- "scriptaddr=0x17000000\0"
+ "fdt_addr_r=0x18200000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=0x18300000\0" \
+ "ramdisk_addr_r=0x18400000\0" \
+ "scriptaddr=0x18280000\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
- "fdt_addr_r=0x82100000\0" \
- "kernel_addr_r=0x81000000\0" \
- "pxefile_addr_r=0x87100000\0" \
- "ramdisk_addr_r=0x82200000\0" \
- "scriptaddr=0x87000000\0"
+ "fdt_addr_r=0x88200000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=0x88300000\0" \
+ "ramdisk_addr_r=0x88400000\0" \
+ "scriptaddr=0x88280000\0"
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
- "fdt_addr_r=0x12100000\0" \
- "kernel_addr_r=0x11000000\0" \
- "pxefile_addr_r=0x17100000\0" \
- "ramdisk_addr_r=0x12200000\0" \
- "scriptaddr=0x17000000\0"
+ "fdt_addr_r=0x18200000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=0x18300000\0" \
+ "ramdisk_addr_r=0x18400000\0" \
+ "scriptaddr=0x18280000\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
- "fdt_addr_r=0x82000000\0" \
- "kernel_addr_r=0x81000000\0" \
- "pxefile_addr_r=0x87100000\0" \
- "ramdisk_addr_r=0x82100000\0" \
- "scriptaddr=0x87000000\0"
+ "fdt_addr_r=0x88200000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=0x88300000\0" \
+ "ramdisk_addr_r=0x88400000\0" \
+ "scriptaddr=0x88280000\0"
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
"update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
"load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\
- "sf probe && sf erase 0x0 0x100000 && " \
- "sf write ${loadaddr} 0x400 ${filesize}\0" \
+ "sf probe && sf update ${loadaddr} 0x400 ${filesize}\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
"fi ; " \
"boot\0" \
"boot_file=fitImage\0" \
- "console=ttymxc1\0" \
+ "console=ttymxc0\0" \
"fdt_addr=0x43000000\0" \
"initrd_addr=0x43800000\0" \
"kernel_image=fitImage\0"
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-/* Totally 6GB DDR */
+/* Totally 2GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
-#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
-#define PHYS_SDRAM_2 0x100000000
-#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
+#define PHYS_SDRAM_SIZE 0x80000000
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2022 Amarula Solutions(India)
+ */
+
+#ifndef __IMX8MP_ICORE_MX8MP_H
+#define __IMX8MP_ICORE_MX8MP_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+#define CONFIG_POWER_PCA9450
+
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_FEC_MXC_PHYADDR 1
+
+#define DWC_NET_PHYADDR 1
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "image=Image\0" \
+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "boot_fdt=try\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "initrd_addr=0x43800000\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+
+/* Totally 2GB DDR */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000
+
+#endif /* __IMX8MP_ICORE_MX8MP_H */
* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
* @CONFIG_KM_PHRAM: address for /var
* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
*/
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE 0x0
/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
* is not valid yet, which is the case for when u-boot copies itself to RAM */
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
* @CONFIG_KM_PHRAM: address for /var
* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
*/
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE 0x0
/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
* is not valid yet, which is the case for when u-boot copies itself to RAM
*/
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x82000000\0" \
- "ramdisk_addr_r=0x88080000\0" \
- "pxefile_addr_r=0x80100000\0" \
- "scriptaddr=0x80100000\0" \
- "bootdelay=3\0" \
- "ethact=" CONFIG_ETHPRIME "\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- BOOTENV
+#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV
#endif /* __KONTRON_MX6UL_CONFIG_H */
#define CONFIG_MALLOC_F_ADDR 0x930000
#endif
-#define ENV_MEM_LAYOUT_SETTINGS \
- "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "kernel_addr_r=0x42000000\0" \
- "fdt_addr_r=0x48000000\0" \
- "fdtoverlay_addr_r=0x49000000\0" \
- "ramdisk_addr_r=0x48080000\0" \
- "scriptaddr=0x40000000\0"\
- "pxefile_addr_r=0x40100000\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
- "bootdelay=3\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV
+#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV
#endif /* __KONTRON_MX8MM_CONFIG_H */
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
- "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
EFI_GUID(0x058b7d83, 0x50d5, 0x4c47, 0xa1, 0x95, \
0x60, 0xd8, 0x6a, 0xd3, 0x41, 0xc4)
+/* Try files from QEMU's -kernel/-initrd, through the QEMU firmware device. */
+#define BOOTENV_DEV_QFW(devtypeu, devtypel, instance) \
+ "bootcmd_qfw= " \
+ "if qfw load $kernel_addr_r $ramdisk_addr_r; then " \
+ " booti $kernel_addr_r $ramdisk_addr_r:$filesize $fdtcontroladdr; " \
+ " if test $? -eq 1; then " \
+ " bootz $kernel_addr_r $ramdisk_addr_r:$filesize $fdtcontroladdr; " \
+ " fi ; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_QFW(devtypeu, devtypel, instance) "qfw "
+
/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
/* Environment options */
#endif
#define BOOT_TARGET_DEVICES(func) \
+ func(QFW, qfw, na) \
BOOT_TARGET_USB(func) \
BOOT_TARGET_SCSI(func) \
BOOT_TARGET_VIRTIO(func) \
"pxefile_addr_r=0x10100000\0" \
"ramdisk_addr_r=0x18080000\0" \
"scriptaddr=0x10000000\0" \
- "set_con_serial=setenv stdout serial; " \
- "setenv stderr serial\0" \
- "set_con_hdmi=setenv stdout serial,vidconsole; " \
- "setenv stderr serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0"
"fdt_addr_r=0x50200000\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_comp_addr_r=0x40200000\0" \
- "kernel_comp_size=0x08080000\0" \
+ "kernel_comp_size=0x08000000\0" \
"ramdisk_addr_r=0x50300000\0" \
"scriptaddr=0x50280000\0"
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-/* ENET */
-#define CONFIG_FEC_MXC_PHYADDR 7
-
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_SYS_I2C
#endif /* CONFIG_SPL_BUILD */
-/* ENET Config */
-/* ENET1 */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_FEC_MXC_PHYADDR 7
-
-#define PHY_ANEG_TIMEOUT 20000
-#endif /* CONFIG_CMD_NET */
-
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x50200000\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_comp_addr_r=0x40200000\0" \
- "kernel_comp_size=0x08080000\0" \
+ "kernel_comp_size=0x08000000\0" \
"ramdisk_addr_r=0x50300000\0" \
"scriptaddr=0x50280000\0"
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_SPDIF_GCLK 164
-#define IMX6SL_CLK_END 165
+#define IMX6SL_CLK_MMDC_P0_IPG 165
+#define IMX6SL_CLK_MMDC_P1_IPG 166
+#define IMX6SL_CLK_END 167
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP.
*
*/
#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
#define IMX6SLL_CLK_EXTERN_AUDIO 172
-#define IMX6SLL_CLK_END 173
+#define IMX6SLL_CLK_GPIO1 173
+#define IMX6SLL_CLK_GPIO2 174
+#define IMX6SLL_CLK_GPIO3 175
+#define IMX6SLL_CLK_GPIO4 176
+#define IMX6SLL_CLK_GPIO5 177
+#define IMX6SLL_CLK_GPIO6 178
+#define IMX6SLL_CLK_MMDC_P1_IPG 179
+
+#define IMX6SLL_CLK_END 180
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017~2018 NXP
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+/* SCG1 */
+
#define IMX7ULP_CLK_DUMMY 0
-#define IMX7ULP_CLK_CKIL 1
-#define IMX7ULP_CLK_OSC 2
+#define IMX7ULP_CLK_ROSC 1
+#define IMX7ULP_CLK_SOSC 2
#define IMX7ULP_CLK_FIRC 3
-
-/* SCG1 */
#define IMX7ULP_CLK_SPLL_PRE_SEL 4
#define IMX7ULP_CLK_SPLL_PRE_DIV 5
#define IMX7ULP_CLK_SPLL 6
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
+#define IMX7ULP_CLK_MIPI_PLL 39
+#define IMX7ULP_CLK_SIRC 40
+#define IMX7ULP_CLK_SOSC_BUS_CLK 41
+#define IMX7ULP_CLK_FIRC_BUS_CLK 42
+#define IMX7ULP_CLK_SPLL_BUS_CLK 43
+#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
+#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
-/* PCG2 */
-#define IMX7ULP_CLK_DMA1 39
-#define IMX7ULP_CLK_RGPIO2P1 40
-#define IMX7ULP_CLK_FLEXBUS 41
-#define IMX7ULP_CLK_SEMA42_1 42
-#define IMX7ULP_CLK_DMA_MUX1 43
-#define IMX7ULP_CLK_SNVS 44
-#define IMX7ULP_CLK_CAAM 45
-#define IMX7ULP_CLK_LPTPM4 46
-#define IMX7ULP_CLK_LPTPM5 47
-#define IMX7ULP_CLK_LPIT1 48
-#define IMX7ULP_CLK_LPSPI2 49
-#define IMX7ULP_CLK_LPSPI3 50
-#define IMX7ULP_CLK_LPI2C4 51
-#define IMX7ULP_CLK_LPI2C5 52
-#define IMX7ULP_CLK_LPUART4 53
-#define IMX7ULP_CLK_LPUART5 54
-#define IMX7ULP_CLK_FLEXIO1 55
-#define IMX7ULP_CLK_USB0 56
-#define IMX7ULP_CLK_USB1 57
-#define IMX7ULP_CLK_USB_PHY 58
-#define IMX7ULP_CLK_USB_PL301 59
-#define IMX7ULP_CLK_USDHC0 60
-#define IMX7ULP_CLK_USDHC1 61
-#define IMX7ULP_CLK_WDG1 62
-#define IMX7ULP_CLK_WDG2 63
-
-/* PCG3 */
-#define IMX7ULP_CLK_LPTPM6 64
-#define IMX7ULP_CLK_LPTPM7 65
-#define IMX7ULP_CLK_LPI2C6 66
-#define IMX7ULP_CLK_LPI2C7 67
-#define IMX7ULP_CLK_LPUART6 68
-#define IMX7ULP_CLK_LPUART7 69
-#define IMX7ULP_CLK_VIU 70
-#define IMX7ULP_CLK_DSI 71
-#define IMX7ULP_CLK_LCDIF 72
-#define IMX7ULP_CLK_MMDC 73
-#define IMX7ULP_CLK_PCTLC 74
-#define IMX7ULP_CLK_PCTLD 75
-#define IMX7ULP_CLK_PCTLE 76
-#define IMX7ULP_CLK_PCTLF 77
-#define IMX7ULP_CLK_GPU3D 78
-#define IMX7ULP_CLK_GPU2D 79
-
-#define IMX7ULP_CLK_MIPI_PLL 80
-#define IMX7ULP_CLK_SIRC 81
+#define IMX7ULP_CLK_CORE 46
+#define IMX7ULP_CLK_HSRUN_CORE 47
-#define IMX7ULP_CLK_SCG1_CLKOUT 82
+#define IMX7ULP_CLK_SCG1_END 48
-#define IMX7ULP_CLK_END 83
+/* PCC2 */
+#define IMX7ULP_CLK_DMA1 0
+#define IMX7ULP_CLK_RGPIO2P1 1
+#define IMX7ULP_CLK_FLEXBUS 2
+#define IMX7ULP_CLK_SEMA42_1 3
+#define IMX7ULP_CLK_DMA_MUX1 4
+#define IMX7ULP_CLK_CAAM 6
+#define IMX7ULP_CLK_LPTPM4 7
+#define IMX7ULP_CLK_LPTPM5 8
+#define IMX7ULP_CLK_LPIT1 9
+#define IMX7ULP_CLK_LPSPI2 10
+#define IMX7ULP_CLK_LPSPI3 11
+#define IMX7ULP_CLK_LPI2C4 12
+#define IMX7ULP_CLK_LPI2C5 13
+#define IMX7ULP_CLK_LPUART4 14
+#define IMX7ULP_CLK_LPUART5 15
+#define IMX7ULP_CLK_FLEXIO1 16
+#define IMX7ULP_CLK_USB0 17
+#define IMX7ULP_CLK_USB1 18
+#define IMX7ULP_CLK_USB_PHY 19
+#define IMX7ULP_CLK_USB_PL301 20
+#define IMX7ULP_CLK_USDHC0 21
+#define IMX7ULP_CLK_USDHC1 22
+#define IMX7ULP_CLK_WDG1 23
+#define IMX7ULP_CLK_WDG2 24
-/*cm4 clocks*/
-#define IMX7ULP_CM4_CLK_DUMMY 0
-#define IMX7ULP_CM4_CLK_CKIL 1
-#define IMX7ULP_CM4_CLK_OSC 2
-#define IMX7ULP_CM4_CLK_FIRC 3
-#define IMX7ULP_CM4_CLK_SIRC 4
+#define IMX7ULP_CLK_PCC2_END 25
-/* SCG0 */
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
-#define IMX7ULP_CM4_CLK_SPLL 7
-#define IMX7ULP_CM4_CLK_SPLL_VCO 8
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
-#define IMX7ULP_CM4_CLK_SPLL_PFD0 11
-#define IMX7ULP_CM4_CLK_SPLL_PFD1 12
-#define IMX7ULP_CM4_CLK_SPLL_PFD2 13
-#define IMX7ULP_CM4_CLK_SPLL_PFD3 14
-#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
-#define IMX7ULP_CM4_CLK_SPLL_PFD 16
-#define IMX7ULP_CM4_CLK_SPLL_SEL 17
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
-#define IMX7ULP_CM4_CLK_APLL 20
-#define IMX7ULP_CM4_CLK_APLL_VCO 21
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
-#define IMX7ULP_CM4_CLK_APLL_PFD0 24
-#define IMX7ULP_CM4_CLK_APLL_PFD1 25
-#define IMX7ULP_CM4_CLK_APLL_PFD2 26
-#define IMX7ULP_CM4_CLK_APLL_PFD3 27
-#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
-#define IMX7ULP_CM4_CLK_APLL_PFD 29
-#define IMX7ULP_CM4_CLK_APLL_SEL 30
-#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
-#define IMX7ULP_CM4_CLK_SYS_SEL 32
-#define IMX7ULP_CM4_CLK_CORE_DIV 33
-#define IMX7ULP_CM4_CLK_BUS_DIV 34
-#define IMX7ULP_CM4_CLK_PLAT_DIV 35
-#define IMX7ULP_CM4_CLK_SLOW_DIV 36
+/* PCC3 */
+#define IMX7ULP_CLK_LPTPM6 0
+#define IMX7ULP_CLK_LPTPM7 1
+#define IMX7ULP_CLK_LPI2C6 2
+#define IMX7ULP_CLK_LPI2C7 3
+#define IMX7ULP_CLK_LPUART6 4
+#define IMX7ULP_CLK_LPUART7 5
+#define IMX7ULP_CLK_VIU 6
+#define IMX7ULP_CLK_DSI 7
+#define IMX7ULP_CLK_LCDIF 8
+#define IMX7ULP_CLK_MMDC 9
+#define IMX7ULP_CLK_PCTLC 10
+#define IMX7ULP_CLK_PCTLD 11
+#define IMX7ULP_CLK_PCTLE 12
+#define IMX7ULP_CLK_PCTLF 13
+#define IMX7ULP_CLK_GPU3D 14
+#define IMX7ULP_CLK_GPU2D 15
-#define IMX7ULP_CM4_CLK_SAI0_SEL 37
-#define IMX7ULP_CM4_CLK_SAI0_DIV 38
-#define IMX7ULP_CM4_CLK_SAI0_ROOT 39
-#define IMX7ULP_CM4_CLK_SAI0_IPG 40
-#define IMX7ULP_CM4_CLK_SAI1_SEL 41
-#define IMX7ULP_CM4_CLK_SAI1_DIV 42
-#define IMX7ULP_CM4_CLK_SAI1_ROOT 43
-#define IMX7ULP_CM4_CLK_SAI1_IPG 44
+#define IMX7ULP_CLK_PCC3_END 16
-#define IMX7ULP_CLK_SCG0_CLKOUT 45
+/* SMC1 */
+#define IMX7ULP_CLK_ARM 0
-#define IMX7ULP_CM4_CLK_END 46
+#define IMX7ULP_CLK_SMC1_END 1
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
};
struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+ u8 ind;
+ u8 val;
};
void enable_layerscape_ns_access(void);
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
- TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP
+ TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI
};
extern char net_boot_file_name[1024];/* Boot File name */
phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}
+bool phy_interface_is_ncsi(void);
+
/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340 0x13e51002
#define PHY_UID_CS4223 0x03e57003
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
+#define SDHCI_QUIRK_SUPPORT_SINGLE (1 << 10)
/* to make gcc happy */
struct sdhci_host;
#include <net.h>
#include <net/fastboot.h>
#include <net/tftp.h>
+#include <net/ncsi.h>
#if defined(CONFIG_CMD_PCAP)
#include <net/pcap.h>
#endif
net_try_count = 1;
debug_cond(DEBUG_INT_STATE, "--- net_loop Entry\n");
+#ifdef CONFIG_PHY_NCSI
+ if (phy_interface_is_ncsi() && protocol != NCSI && !ncsi_active()) {
+ printf("%s: configuring NCSI first\n", __func__);
+ if (net_loop(NCSI) < 0)
+ return ret;
+ eth_init_state_only();
+ goto restart;
+ }
+#endif
+
bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
net_init();
if (eth_is_on_demand_init()) {
} else {
eth_init_state_only();
}
+
restart:
#ifdef CONFIG_USB_KEYBOARD
net_busy_flag = 0;
wol_start();
break;
#endif
+#if defined(CONFIG_PHY_NCSI)
+ case NCSI:
+ ncsi_probe_packages();
+ break;
+#endif
default:
break;
}
env_set_hex("filesize", net_boot_file_size);
env_set_hex("fileaddr", image_load_addr);
}
- if (protocol != NETCONS)
+ if (protocol != NETCONS && protocol != NCSI)
eth_halt();
else
eth_halt_state_only();
wol_receive(ip, len);
break;
#endif
+#ifdef CONFIG_PHY_NCSI
+ case PROT_NCSI:
+ ncsi_receive(et, ip, len);
+ break;
+#endif
}
}
#ifdef CONFIG_CMD_RARP
case RARP:
#endif
+#ifdef CONFIG_PHY_NCSI
+ case NCSI:
+#endif
case BOOTP:
case CDP:
case DHCP:
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
CONFIG_KM_ECC_MODE
CONFIG_KM_NEW_ENV
-CONFIG_KM_ROOTFSSIZE
CONFIG_KM_UBI_LINUX_MTD
CONFIG_KM_UBI_PARTITION_NAME_APP
CONFIG_KM_UBI_PARTITION_NAME_BOOT
run_test "sandbox_spl" ./test/py/test.py --bd sandbox_spl --build ${para} \
-k 'test_ofplatdata or test_handoff or test_spl'
-# Run the sane tests with sandbox_noinst (i.e. without OF_PLATDATA_INST)
+# Run the same tests with sandbox_noinst (i.e. without OF_PLATDATA_INST)
echo "${prompt}"
-run_test "sandbox_spl" ./test/py/test.py --bd sandbox_noinst --build ${para} \
+run_test "sandbox_noinst" ./test/py/test.py --bd sandbox_noinst --build ${para} \
-k 'test_ofplatdata or test_handoff or test_spl'
if [ -z "$tools_only" ]; then
projects / platform / kernel / u-boot.git / commitdiff