return 0;
}
- virtual bool isADD64rr(const MCInst &Inst) const {
- llvm_unreachable("not implemented");
- return false;
- }
-
virtual bool isSUB(const MCInst &Inst) const {
llvm_unreachable("not implemented");
return false;
bool isMoveMem2Reg(const MCInst &Inst) const override { return false; }
- bool isADD64rr(const MCInst &Inst) const override { return false; }
-
bool isLeave(const MCInst &Inst) const override { return false; }
bool isPop(const MCInst &Inst) const override { return false; }
return Inst.getOpcode() == X86::MOVSX64rm32;
}
+bool isADD64rr(const MCInst &Inst) { return Inst.getOpcode() == X86::ADD64rr; }
+
+bool isADDri(const MCInst &Inst) {
+ return Inst.getOpcode() == X86::ADD64ri32 ||
+ Inst.getOpcode() == X86::ADD64ri8;
+}
+
class X86MCPlusBuilder : public MCPlusBuilder {
public:
X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info,
return 0;
}
- bool isADD64rr(const MCInst &Inst) const override {
- return Inst.getOpcode() == X86::ADD64rr;
- }
-
bool isSUB(const MCInst &Inst) const override {
return X86::isSUB(Inst.getOpcode());
}
- bool isADDri(const MCInst &Inst) const {
- return Inst.getOpcode() == X86::ADD64ri32 ||
- Inst.getOpcode() == X86::ADD64ri8;
- }
-
bool isLEA64r(const MCInst &Inst) const override {
return Inst.getOpcode() == X86::LEA64r;
}