Add SFENCE.VMA instruction

include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.

diff --git a/include/ChangeLog b/include/ChangeLog
index e90166c..7e59ea2 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-14  Andrew Waterman  <andrew@sifive.com>
+
+       * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
+       (MASK_SFENCE_VMA): Likewise.
+       (sfence_vma): Declare instruction.
+
 2017-02-14  Alan Modra  <amodra@gmail.com>
 
        PR 21118

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 09d680b..dd58053 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -227,6 +227,8 @@
 #define MASK_DRET  0xffffffff
 #define MATCH_SFENCE_VM 0x10400073
 #define MASK_SFENCE_VM  0xfff07fff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
 #define MATCH_WFI 0x10500073
 #define MASK_WFI  0xffffffff
 #define MATCH_CSRRW 0x1073
@@ -883,6 +885,7 @@ DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4e58d6c..8830698 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-14  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
+       pseudoinstructions.
+
 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 
        * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cc39390..61d0159 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -678,6 +678,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"dret",      "I",   "",     MATCH_DRET, MASK_DRET, match_opcode, 0 },
 {"sfence.vm", "I",   "",     MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
 {"sfence.vm", "I",   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
+{"sfence.vma","I",   "",     MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS1 | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I",   "s",    MATCH_SFENCE_VMA, MASK_SFENCE_VMA | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sfence.vma","I",   "s,t",  MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
 {"wfi",       "I",   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
 
 /* Terminate the list.  */