PD#166793: code defects in clk part
Change-Id: Iee2753552c6f345ea78329833415e607b141d188
Signed-off-by: zhiqiang.liang <zhiqiang.liang@amlogic.com>
premux = rate_set->premux;
best_parent = clk_hw_get_parent_by_index(hw, premux);
+
+ if (!best_parent)
+ return -EINVAL;
+
best = clk_hw_get_rate(best_parent);
if (best != parent_req.rate)
meson_fclk_cpu_set_parent(hw, premux);
- if (!best_parent)
- return -EINVAL;
-
if (best_parent)
req->best_parent_hw = best_parent;
struct scpi_clk *) = data;
struct clk_onecell_data *clk_data;
struct clk **clks;
- size_t count;
+ int count;
int idx;
count = of_property_count_strings(np, "clock-output-names");
p = &pll->frac;
- if (p->width) {
+ if (p->width >= 2) {
reg = readl(pll->base + p->reg_off);
frac = PARM_GET(p->width - 1, p->shift, reg);