Clk: clean the coverity errors of clk module
authorzhiqiang.liang <zhiqiang.liang@amlogic.com>
Tue, 21 Aug 2018 08:44:23 +0000 (16:44 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Tue, 21 Aug 2018 11:37:06 +0000 (04:37 -0700)
PD#166793: code defects in clk part

Change-Id: Iee2753552c6f345ea78329833415e607b141d188
Signed-off-by: zhiqiang.liang <zhiqiang.liang@amlogic.com>
drivers/amlogic/clk/clk-cpu-fclk-composite.c
drivers/amlogic/clk/clk-scpi.c
drivers/amlogic/clk/g12a/g12a_clk-pll.c

index cfe9618..ba722e5 100644 (file)
@@ -274,14 +274,15 @@ int meson_fclk_mux_divider_determine_rate(struct clk_hw *hw,
 
        premux = rate_set->premux;
        best_parent = clk_hw_get_parent_by_index(hw, premux);
+
+       if (!best_parent)
+               return -EINVAL;
+
        best = clk_hw_get_rate(best_parent);
 
        if (best != parent_req.rate)
                meson_fclk_cpu_set_parent(hw, premux);
 
-       if (!best_parent)
-               return -EINVAL;
-
        if (best_parent)
                req->best_parent_hw = best_parent;
 
index 33294d5..501b8a4 100644 (file)
@@ -198,7 +198,7 @@ static int scpi_clk_setup(struct device *dev, struct device_node *np,
                                 struct scpi_clk *) = data;
        struct clk_onecell_data *clk_data;
        struct clk **clks;
-       size_t count;
+       int count;
        int idx;
 
        count = of_property_count_strings(np, "clock-output-names");
index 929477c..7e2c21d 100644 (file)
@@ -123,7 +123,7 @@ static unsigned long meson_g12a_pll_recalc_rate(struct clk_hw *hw,
 
        p = &pll->frac;
 
-       if (p->width) {
+       if (p->width >= 2) {
                reg = readl(pll->base + p->reg_off);
                frac = PARM_GET(p->width - 1, p->shift, reg);