(define_insn "addsubv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
- (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
- (parallel [(const_int 0)])))
- (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
- ""
- "%0 = %1 +|- %2%!"
- [(set_attr "type" "dsp32")])
-
-(define_insn "subaddv2hi3"
- [(set (match_operand:V2HI 0 "register_operand" "=d")
- (vec_concat:V2HI
(minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
(parallel [(const_int 0)]))
(vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
(plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
- "%0 = %1 -|+ %2%!"
+ "%0 = %1 +|- %2%!"
[(set_attr "type" "dsp32")])
-(define_insn "ssaddsubv2hi3"
+(define_insn "subaddv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
- (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
- (parallel [(const_int 0)])))
- (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+ (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+ (parallel [(const_int 0)]))
+ (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+ (parallel [(const_int 0)])))
+ (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+ (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
- "%0 = %1 +|- %2 (S)%!"
+ "%0 = %1 -|+ %2%!"
[(set_attr "type" "dsp32")])
-(define_insn "sssubaddv2hi3"
+(define_insn "ssaddsubv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
(ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
(ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
+ "%0 = %1 +|- %2 (S)%!"
+ [(set_attr "type" "dsp32")])
+
+(define_insn "sssubaddv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=d")
+ (vec_concat:V2HI
+ (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+ (parallel [(const_int 0)]))
+ (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+ (parallel [(const_int 0)])))
+ (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+ (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+ ""
"%0 = %1 -|+ %2 (S)%!"
[(set_attr "type" "dsp32")])