static int vce_v2_0_stop(struct amdgpu_device *adev)
{
- int i, j;
+ int i;
int status;
if (vce_v2_0_lmi_clean(adev)) {
DRM_INFO("vce is not idle \n");
return 0;
}
-/*
- for (i = 0; i < 10; ++i) {
- for (j = 0; j < 100; ++j) {
- status = RREG32(mmVCE_FW_REG_STATUS);
- if (!(status & 1))
- break;
- mdelay(1);
- }
- break;
- }
-*/
+
if (vce_v2_0_wait_for_idle(adev)) {
DRM_INFO("VCE is busy, Can't set clock gateing");
return 0;
/* Stall UMC and register bus before resetting VCPU */
WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
- for (i = 0; i < 10; ++i) {
- for (j = 0; j < 100; ++j) {
- status = RREG32(mmVCE_LMI_STATUS);
- if (status & 0x240)
- break;
- mdelay(1);
- }
- break;
+ for (i = 0; i < 100; ++i) {
+ status = RREG32(mmVCE_LMI_STATUS);
+ if (status & 0x240)
+ break;
+ mdelay(1);
}
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);