(SIM_RC)
sim_core_init (SIM_DESC sd)
{
- sim_core *memory = STATE_CORE(sd);
+ sim_core *core = STATE_CORE(sd);
sim_core_maps map;
- for (map = 0;
- map < nr_sim_core_maps;
- map++) {
+ for (map = 0; map < nr_sim_core_maps; map++) {
/* blow away old mappings */
- sim_core_mapping *curr = memory->map[map].first;
+ sim_core_mapping *curr = core->common.map[map].first;
while (curr != NULL) {
sim_core_mapping *tbd = curr;
curr = curr->next;
}
zfree(tbd);
}
- memory->map[map].first = NULL;
+ core->common.map[map].first = NULL;
+ }
+ core->byte_xor = 0;
+ /* Just copy this map to each of the processor specific data structures.
+ FIXME - later this will be replaced by true processor specific
+ maps. */
+ {
+ int i;
+ for (i = 0; i < MAX_NR_PROCESSORS; i++)
+ {
+ int j;
+ CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
+ for (j = 0; j < WITH_XOR_ENDIAN; j++)
+ CPU_CORE (STATE_CPU (sd, i))->xor [j] = 0;
+ }
}
return SIM_RC_OK;
}
next_mapping = access_map->first;
last_mapping = &access_map->first;
while(next_mapping != NULL
- && (next_mapping->level < attach
- || (next_mapping->level == attach
+ && (next_mapping->level < (int) attach
+ || (next_mapping->level == (int) attach
&& next_mapping->bound < addr))) {
/* provided levels are the same */
/* assert: next_mapping->base > all bases before next_mapping */
}
/* check insertion point correct */
- SIM_ASSERT(next_mapping == NULL || next_mapping->level >= attach);
- if (next_mapping != NULL && next_mapping->level == attach
+ SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach);
+ if (next_mapping != NULL && next_mapping->level == (int) attach
&& next_mapping->base < (addr + (nr_bytes - 1))) {
#if (WITH_DEVICES)
device_error(client, "map overlap when attaching %d:0x%lx (%ld)",
sim_core_maps map;
void *buffer;
int buffer_freed;
- int i;
/* check for for attempt to use unimplemented per-processor core map */
if (cpu != NULL)
switch (map) {
case sim_core_read_map:
if (access & access_read)
- sim_core_map_attach(sd, &memory->map[map],
- attach,
- space, addr, nr_bytes,
- client, buffer, !buffer_freed);
+ sim_core_map_attach(sd, &memory->common.map[map],
+ attach,
+ space, addr, nr_bytes,
+ client, buffer, !buffer_freed);
buffer_freed ++;
break;
case sim_core_write_map:
if (access & access_write)
- sim_core_map_attach(sd, &memory->map[map],
+ sim_core_map_attach(sd, &memory->common.map[map],
attach,
space, addr, nr_bytes,
client, buffer, !buffer_freed);
break;
case sim_core_execute_map:
if (access & access_exec)
- sim_core_map_attach(sd, &memory->map[map],
+ sim_core_map_attach(sd, &memory->common.map[map],
attach,
space, addr, nr_bytes,
client, buffer, !buffer_freed);
/* Just copy this map to each of the processor specific data structures.
FIXME - later this will be replaced by true processor specific
maps. */
- for (i = 0; i < MAX_NR_PROCESSORS; i++)
- {
- CPU_CORE (STATE_CPU (sd, i))->common = *STATE_CORE (sd);
- }
+ {
+ int i;
+ for (i = 0; i < MAX_NR_PROCESSORS; i++)
+ {
+ CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
+ }
+ }
}
STATIC_INLINE_SIM_CORE\
(sim_core_mapping *)
-sim_core_find_mapping(sim_core *core,
+sim_core_find_mapping(sim_core_common *core,
sim_core_maps map,
address_word addr,
unsigned nr_bytes,
STATIC_INLINE_SIM_CORE\
(void *)
-sim_core_translate(sim_core_mapping *mapping,
- address_word addr)
+sim_core_translate (sim_core_mapping *mapping,
+ address_word addr)
{
return (void *)(((char *)mapping->buffer) + addr - mapping->base);
}
EXTERN_SIM_CORE\
(unsigned)
-sim_core_read_buffer(SIM_DESC sd,
- sim_core_maps map,
- void *buffer,
- address_word addr,
- unsigned len)
+sim_core_read_buffer (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_core_maps map,
+ void *buffer,
+ address_word addr,
+ unsigned len)
{
+ sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
unsigned count = 0;
while (count < len) {
unsigned_word raddr = addr + count;
sim_core_mapping *mapping =
- sim_core_find_mapping(STATE_CORE (sd), map,
+ sim_core_find_mapping(core, map,
raddr, /*nr-bytes*/1,
read_transfer,
- 0, NULL, NULL_CIA); /*dont-abort*/
+ 0 /*dont-abort*/, NULL, NULL_CIA);
if (mapping == NULL)
break;
#if (WITH_DEVICES)
EXTERN_SIM_CORE\
(unsigned)
-sim_core_write_buffer(SIM_DESC sd,
- sim_core_maps map,
- const void *buffer,
- address_word addr,
- unsigned len)
+sim_core_write_buffer (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_core_maps map,
+ const void *buffer,
+ address_word addr,
+ unsigned len)
{
+ sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
unsigned count = 0;
while (count < len) {
unsigned_word raddr = addr + count;
- sim_core_mapping *mapping = sim_core_find_mapping(STATE_CORE (sd), map,
- raddr, /*nr-bytes*/1,
- write_transfer,
- 0, NULL, NULL_CIA); /*dont-abort*/
+ sim_core_mapping *mapping =
+ sim_core_find_mapping(core, map,
+ raddr, /*nr-bytes*/1,
+ write_transfer,
+ 0 /*dont-abort*/, NULL, NULL_CIA);
if (mapping == NULL)
break;
#if (WITH_DEVICES)
EXTERN_SIM_CORE\
(void)
-sim_core_set_xor (sim_cpu *cpu,
- sim_cia cia,
+sim_core_set_xor (SIM_DESC sd,
+ sim_cpu *cpu,
int is_xor)
{
- sim_cpu_core *cpu_core = CPU_CORE (cpu);
- /* set up the XOR registers if required. */
+ /* set up the XOR map if required. */
if (WITH_XOR_ENDIAN) {
{
- int i = 1;
- unsigned mask;
- if (is_xor)
- mask = WITH_XOR_ENDIAN - 1;
- else
- mask = 0;
- while (i - 1 < WITH_XOR_ENDIAN)
+ sim_core *core = STATE_CORE (sd);
+ sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
+ if (cpu_core != NULL)
{
- cpu_core->xor[i-1] = mask;
- mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
- i = (i << 1);
+ int i = 1;
+ unsigned mask;
+ if (is_xor)
+ mask = WITH_XOR_ENDIAN - 1;
+ else
+ mask = 0;
+ while (i - 1 < WITH_XOR_ENDIAN)
+ {
+ cpu_core->xor[i-1] = mask;
+ mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
+ i = (i << 1);
+ }
}
+ else
+ {
+ if (is_xor)
+ core->byte_xor = WITH_XOR_ENDIAN - 1;
+ else
+ core->byte_xor = 0;
+ }
}
}
else {
if (is_xor)
- sim_engine_abort (CPU_STATE (cpu), cpu, cia,
+ sim_engine_abort (sd, cpu, NULL_CIA,
"Attempted to enable xor-endian mode when permenantly disabled.");
}
}
+STATIC_INLINE_SIM_CORE\
+(void)
+reverse_n (unsigned_1 *dest,
+ const unsigned_1 *src,
+ int nr_bytes)
+{
+ int i;
+ for (i = 0; i < nr_bytes; i++)
+ {
+ dest [nr_bytes - i - 1] = src [i];
+ }
+}
+
+
+EXTERN_SIM_CORE\
+(unsigned)
+sim_core_xor_read_buffer (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_core_maps map,
+ void *buffer,
+ address_word addr,
+ unsigned nr_bytes)
+{
+ address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
+ if (!WITH_XOR_ENDIAN || !byte_xor)
+ return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
+ else
+ /* only break up transfers when xor-endian is both selected and enabled */
+ {
+ unsigned_1 x[WITH_XOR_ENDIAN];
+ unsigned nr_transfered = 0;
+ address_word start = addr;
+ unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
+ address_word stop;
+ /* initial and intermediate transfers are broken when they cross
+ an XOR endian boundary */
+ while (nr_transfered + nr_this_transfer < nr_bytes)
+ /* initial/intermediate transfers */
+ {
+ /* since xor-endian is enabled stop^xor defines the start
+ address of the transfer */
+ stop = start + nr_this_transfer - 1;
+ SIM_ASSERT (start <= stop);
+ SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
+ if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
+ != nr_this_transfer)
+ return nr_transfered;
+ reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
+ nr_transfered += nr_this_transfer;
+ nr_this_transfer = WITH_XOR_ENDIAN;
+ start = stop + 1;
+ }
+ /* final transfer */
+ nr_this_transfer = nr_bytes - nr_transfered;
+ stop = start + nr_this_transfer - 1;
+ SIM_ASSERT (stop == (addr + nr_bytes - 1));
+ if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
+ != nr_this_transfer)
+ return nr_transfered;
+ reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
+ return nr_bytes;
+ }
+}
+
+
+EXTERN_SIM_CORE\
+(unsigned)
+sim_core_xor_write_buffer (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_core_maps map,
+ const void *buffer,
+ address_word addr,
+ unsigned nr_bytes)
+{
+ address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
+ if (!WITH_XOR_ENDIAN || !byte_xor)
+ return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
+ else
+ /* only break up transfers when xor-endian is both selected and enabled */
+ {
+ unsigned_1 x[WITH_XOR_ENDIAN];
+ unsigned nr_transfered = 0;
+ address_word start = addr;
+ unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
+ address_word stop;
+ /* initial and intermediate transfers are broken when they cross
+ an XOR endian boundary */
+ while (nr_transfered + nr_this_transfer < nr_bytes)
+ /* initial/intermediate transfers */
+ {
+ /* since xor-endian is enabled stop^xor defines the start
+ address of the transfer */
+ stop = start + nr_this_transfer - 1;
+ SIM_ASSERT (start <= stop);
+ SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
+ reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
+ if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
+ != nr_this_transfer)
+ return nr_transfered;
+ nr_transfered += nr_this_transfer;
+ nr_this_transfer = WITH_XOR_ENDIAN;
+ start = stop + 1;
+ }
+ /* final transfer */
+ nr_this_transfer = nr_bytes - nr_transfered;
+ stop = start + nr_this_transfer - 1;
+ SIM_ASSERT (stop == (addr + nr_bytes - 1));
+ reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
+ if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
+ != nr_this_transfer)
+ return nr_transfered;
+ return nr_bytes;
+ }
+}
-/* Simulator Floating-point support.
- Copyright (C) 1994, 1997 Free Software Foundation, Inc.
- Contributed by Cygnus Support.
+/* This is a software floating point library which can be used instead of
+ the floating point routines in libgcc1.c for targets without hardware
+ floating point. */
-This file is part of GDB, the GNU debugger.
+/* Copyright (C) 1994,1997 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file. (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+/* As a special exception, if you link this library with other files,
+ some of which are compiled with GCC, to produce an executable,
+ this library does not by itself cause the resulting executable
+ to be covered by the GNU General Public License.
+ This exception does not however invalidate any other reasons why
+ the executable file might be covered by the GNU General Public License. */
+
+/* This implements IEEE 754 format arithmetic, but does not provide a
+ mechanism for setting the rounding mode, or for generating or handling
+ exceptions.
+
+ The original code by Steve Chamberlain, hacked by Mark Eichin and Jim
+ Wilson, all of Cygnus Support. */
#ifndef SIM_FPU_C
#define SP_NGARDS 7L
#define SP_GARDROUND 0x3f
-#define SP_GARDMASK 0x7f
-#define SP_GARDMSB 0x40
+#define SP_GARDMASK ((unsigned) 0x7f)
+#define SP_GARDMSB ((unsigned) 0x40)
#define SP_EXPBITS 8
#define SP_EXPBIAS 127
#define SP_FRACBITS 23
-#define SP_EXPMAX (0xff)
+#define SP_EXPMAX ((unsigned) 0xff)
#define SP_QUIET_NAN 0x100000L
#define SP_FRAC_NBITS 32
#define SP_FRACHIGH 0x80000000L
#define DP_NGARDS 8L
#define DP_GARDROUND 0x7f
-#define DP_GARDMASK 0xff
-#define DP_GARDMSB 0x80
+#define DP_GARDMASK ((unsigned) 0xff)
+#define DP_GARDMSB ((unsigned) 0x80)
#define DP_EXPBITS 11
#define DP_EXPBIAS 1023
#define DP_FRACBITS 52
-#define DP_EXPMAX (0x7ff)
-#define DP_QUIET_NAN 0x8000000000000LL
+#define DP_EXPMAX ((unsigned) 0x7ff)
+#define DP_QUIET_NAN MSBIT64 (12) /* 0x0008000000000000LL */
#define DP_FRAC_NBITS 64
-#define DP_FRACHIGH 0x8000000000000000LL
-#define DP_FRACHIGH2 0xc000000000000000LL
+#define DP_FRACHIGH MSMASK64 (1) /* 0x8000000000000000LL */
+#define DP_FRACHIGH2 MSMASK64 (2) /* 0xc000000000000000LL */
#define EXPMAX (is_double ? DP_EXPMAX : SP_EXPMAX)
#define EXPBITS (is_double ? DP_EXPBITS : SP_EXPBITS)
#define EXPBIAS (is_double ? DP_EXPBIAS : SP_EXPBIAS)
#define FRACBITS (is_double ? DP_FRACBITS : SP_FRACBITS)
#define NGARDS (is_double ? DP_NGARDS : (SP_NGARDS ))
-#define SIGNBIT (1LL << (EXPBITS + FRACBITS))
+#define SIGNBIT ((unsigned64)1 << (EXPBITS + FRACBITS))
#define FRAC_NBITS (is_double ? DP_FRAC_NBITS : SP_FRAC_NBITS)
#define GARDMASK (is_double ? DP_GARDMASK : SP_GARDMASK)
#define GARDMSB (is_double ? DP_GARDMSB : SP_GARDMSB)
#define NORMAL_EXPMIN (-(EXPBIAS)+1)
-#define IMPLICIT_1 (1LL<<(FRACBITS+NGARDS))
-#define IMPLICIT_2 (1LL<<(FRACBITS+1+NGARDS))
+#define IMPLICIT_1 ((unsigned64)1 << (FRACBITS+NGARDS))
+#define IMPLICIT_2 ((unsigned64)1 << (FRACBITS+1+NGARDS))
#define MAX_SI_INT (is_double ? LSMASK64 (63) : LSMASK64 (31))
#define MAX_USI_INT (is_double ? LSMASK64 (64) : LSMASK64 (32))
return ans;
}
+#if 0
STATIC_INLINE_SIM_FPU (int)
is_ufpu_number (const sim_ufpu *d)
{
return 0;
}
}
+#endif
STATIC_INLINE_SIM_FPU (int)
projects / external / binutils.git / commitdiff