ARM: dts: Renesas R9A06G032 SMP enable method

Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 339d0958011e4e1a63e3af7fd88af7e69e85a519..afe29c95a006e8fa12d0ed66f5948e8ac1a17262 100644 (file)
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -29,6 +29,8 @@
                        compatible = "arm,cortex-a7";
                        reg = <1>;
                        clocks = <&sysctrl 84>;
+                       enable-method = "renesas,r9a06g032-smp";
+                       cpu-release-addr = <0 0x4000c204>;
                };
        };