* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_32(0, fn, sfx), \
- PORT_GP_30(1, fn, sfx), \
- PORT_GP_30(2, fn, sfx), \
- PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_32(4, fn, sfx), \
- PORT_GP_32(5, fn, sfx)
+ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP(IIC0_SDA, "AF15", fn), \
PIN_NOGP(IIC0_SCL, "AG15", fn), \
PIN_NOGP(IIC3_SDA, "AH15", fn), \
- PIN_NOGP(IIC3_SCL, "AJ15", fn)
+ PIN_NOGP(IIC3_SCL, "AJ15", fn), \
+ PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
- FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+ FN_WE0_N, FN_IECLK, FN_CAN_CLK,
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
- FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+ FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
FN_SSI_WS78_B,
/* IPSR6 */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+ FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
- FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+ FN_SSI_WS6_B, FN_SSI_SDATA8_C,
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
- FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+ FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
- INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+ WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
- IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+ IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
SSI_WS78_B_MARK,
- DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+ DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
- INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+ SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
- MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+ MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
- PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
- PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
- PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
- PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
- PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
#endif /* CONFIG_PINCTRL_PFC_R8A7790 */
/* - MMCIF0 ----------------------------------------------------------------- */
-static const unsigned int mmc0_data1_pins[] = {
- /* D[0] */
- RCAR_GP_PIN(3, 18),
-};
-static const unsigned int mmc0_data1_mux[] = {
- MMC0_D0_MARK,
-};
-static const unsigned int mmc0_data4_pins[] = {
- /* D[0:3] */
- RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
- RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
-};
-static const unsigned int mmc0_data4_mux[] = {
- MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
-};
-static const unsigned int mmc0_data8_pins[] = {
+static const unsigned int mmc0_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
};
-static const unsigned int mmc0_data8_mux[] = {
+static const unsigned int mmc0_data_mux[] = {
MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
};
MMC0_CLK_MARK, MMC0_CMD_MARK,
};
/* - MMCIF1 ----------------------------------------------------------------- */
-static const unsigned int mmc1_data1_pins[] = {
- /* D[0] */
- RCAR_GP_PIN(3, 26),
-};
-static const unsigned int mmc1_data1_mux[] = {
- MMC1_D0_MARK,
-};
-static const unsigned int mmc1_data4_pins[] = {
- /* D[0:3] */
- RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
- RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
-};
-static const unsigned int mmc1_data4_mux[] = {
- MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
-};
-static const unsigned int mmc1_data8_pins[] = {
+static const unsigned int mmc1_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
-static const unsigned int mmc1_data8_mux[] = {
+static const unsigned int mmc1_data_mux[] = {
MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
};
static const unsigned int qspi_ctrl_mux[] = {
SPCLK_MARK, SSL_MARK,
};
-static const unsigned int qspi_data2_pins[] = {
- /* MOSI_IO0, MISO_IO1 */
- RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
-};
-static const unsigned int qspi_data2_mux[] = {
- MOSI_IO0_MARK, MISO_IO1_MARK,
-};
-static const unsigned int qspi_data4_pins[] = {
+static const unsigned int qspi_data_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(1, 8),
};
-static const unsigned int qspi_data4_mux[] = {
+static const unsigned int qspi_data_mux[] = {
MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
- SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 10),
-};
-static const unsigned int sdhi1_data1_mux[] = {
- SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
};
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 18),
-};
-static const unsigned int sdhi2_data1_mux[] = {
- SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
};
-static const unsigned int sdhi2_data4_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
SD2_WP_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 26),
-};
-static const unsigned int sdhi3_data1_mux[] = {
- SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
};
-static const unsigned int sdhi3_data4_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
};
static const unsigned int sdhi3_ctrl_pins[] = {
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
- /* PWEN, OVC/VBUS */
- RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
+ /* OVC/VBUS, PWEN */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
};
static const unsigned int usb0_mux[] = {
- USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
-};
-static const unsigned int usb0_ovc_vbus_pins[] = {
- /* OVC/VBUS */
- RCAR_GP_PIN(5, 19),
-};
-static const unsigned int usb0_ovc_vbus_mux[] = {
- USB0_OVC_VBUS_MARK,
+ USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
-static const unsigned int usb1_pwen_pins[] = {
- /* PWEN */
- RCAR_GP_PIN(5, 20),
-};
-static const unsigned int usb1_pwen_mux[] = {
- USB1_PWEN_MARK,
-};
/* - USB2 ------------------------------------------------------------------- */
static const unsigned int usb2_pins[] = {
/* PWEN, OVC */
USB2_PWEN_MARK, USB2_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
-static const union vin_data vin0_data_pins = {
- .data24 = {
- /* B */
- RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
- RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
- RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
- RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
- /* G */
- RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
- RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
- RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
- RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
- /* R */
- RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
- RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
- RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
- RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
- },
+static const unsigned int vin0_data_pins[] = {
+ /* B */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* G */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ /* R */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+ RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
};
-static const union vin_data vin0_data_mux = {
- .data24 = {
- /* B */
- VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
- VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
- VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
- VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
- /* G */
- VI0_G0_MARK, VI0_G1_MARK,
- VI0_G2_MARK, VI0_G3_MARK,
- VI0_G4_MARK, VI0_G5_MARK,
- VI0_G6_MARK, VI0_G7_MARK,
- /* R */
- VI0_R0_MARK, VI0_R1_MARK,
- VI0_R2_MARK, VI0_R3_MARK,
- VI0_R4_MARK, VI0_R5_MARK,
- VI0_R6_MARK, VI0_R7_MARK,
- },
+static const unsigned int vin0_data_mux[] = {
+ /* B */
+ VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
+ VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
+ VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+ VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+ /* G */
+ VI0_G0_MARK, VI0_G1_MARK,
+ VI0_G2_MARK, VI0_G3_MARK,
+ VI0_G4_MARK, VI0_G5_MARK,
+ VI0_G6_MARK, VI0_G7_MARK,
+ /* R */
+ VI0_R0_MARK, VI0_R1_MARK,
+ VI0_R2_MARK, VI0_R3_MARK,
+ VI0_R4_MARK, VI0_R5_MARK,
+ VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_data18_pins[] = {
/* B */
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
-static const union vin_data vin1_data_pins = {
- .data24 = {
- /* B */
- RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
- RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
- RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
- RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
- /* G */
- RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
- RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
- RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
- RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
- /* R */
- RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
- RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
- RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
- RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
- },
+static const unsigned int vin1_data_pins[] = {
+ /* B */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+ /* G */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
};
-static const union vin_data vin1_data_mux = {
- .data24 = {
- /* B */
- VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
- VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
- VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
- VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
- /* G */
- VI1_G0_MARK, VI1_G1_MARK,
- VI1_G2_MARK, VI1_G3_MARK,
- VI1_G4_MARK, VI1_G5_MARK,
- VI1_G6_MARK, VI1_G7_MARK,
- /* R */
- VI1_R0_MARK, VI1_R1_MARK,
- VI1_R2_MARK, VI1_R3_MARK,
- VI1_R4_MARK, VI1_R5_MARK,
- VI1_R6_MARK, VI1_R7_MARK,
- },
+static const unsigned int vin1_data_mux[] = {
+ /* B */
+ VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
+ VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
+ VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+ VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+ /* G */
+ VI1_G0_MARK, VI1_G1_MARK,
+ VI1_G2_MARK, VI1_G3_MARK,
+ VI1_G4_MARK, VI1_G5_MARK,
+ VI1_G6_MARK, VI1_G7_MARK,
+ /* R */
+ VI1_R0_MARK, VI1_R1_MARK,
+ VI1_R2_MARK, VI1_R3_MARK,
+ VI1_R4_MARK, VI1_R5_MARK,
+ VI1_R6_MARK, VI1_R7_MARK,
};
static const unsigned int vin1_data18_pins[] = {
/* B */
VI1_R4_MARK, VI1_R5_MARK,
VI1_R6_MARK, VI1_R7_MARK,
};
-static const union vin_data vin1_data_b_pins = {
- .data24 = {
- /* B */
- RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
- RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
- RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
- RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
- /* G */
- RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
- RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
- RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
- RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
- /* R */
- RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
- RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
- RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
- RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
- },
+static const unsigned int vin1_data_b_pins[] = {
+ /* B */
+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ /* G */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
};
-static const union vin_data vin1_data_b_mux = {
- .data24 = {
- /* B */
- VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
- VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
- VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
- VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
- /* G */
- VI1_G0_B_MARK, VI1_G1_B_MARK,
- VI1_G2_B_MARK, VI1_G3_B_MARK,
- VI1_G4_B_MARK, VI1_G5_B_MARK,
- VI1_G6_B_MARK, VI1_G7_B_MARK,
- /* R */
- VI1_R0_B_MARK, VI1_R1_B_MARK,
- VI1_R2_B_MARK, VI1_R3_B_MARK,
- VI1_R4_B_MARK, VI1_R5_B_MARK,
- VI1_R6_B_MARK, VI1_R7_B_MARK,
- },
+static const unsigned int vin1_data_b_mux[] = {
+ /* B */
+ VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+ VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+ VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+ VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
+ /* G */
+ VI1_G0_B_MARK, VI1_G1_B_MARK,
+ VI1_G2_B_MARK, VI1_G3_B_MARK,
+ VI1_G4_B_MARK, VI1_G5_B_MARK,
+ VI1_G6_B_MARK, VI1_G7_B_MARK,
+ /* R */
+ VI1_R0_B_MARK, VI1_R1_B_MARK,
+ VI1_R2_B_MARK, VI1_R3_B_MARK,
+ VI1_R4_B_MARK, VI1_R5_B_MARK,
+ VI1_R6_B_MARK, VI1_R7_B_MARK,
};
static const unsigned int vin1_data18_b_pins[] = {
/* B */
VI1_CLK_B_MARK,
};
/* - VIN2 ----------------------------------------------------------------- */
-static const union vin_data vin2_data_pins = {
- .data24 = {
- /* B */
- RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
- RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
- RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
- RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
- /* G */
- RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
- RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
- RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
- /* R */
- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
- RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
- RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
- RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
- },
-};
-static const union vin_data vin2_data_mux = {
- .data24 = {
- /* B */
- VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
- VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
- VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
- VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
- /* G */
- VI2_G0_MARK, VI2_G1_MARK,
- VI2_G2_MARK, VI2_G3_MARK,
- VI2_G4_MARK, VI2_G5_MARK,
- VI2_G6_MARK, VI2_G7_MARK,
- /* R */
- VI2_R0_MARK, VI2_R1_MARK,
- VI2_R2_MARK, VI2_R3_MARK,
- VI2_R4_MARK, VI2_R5_MARK,
- VI2_R6_MARK, VI2_R7_MARK,
- },
-};
-static const unsigned int vin2_data18_pins[] = {
+static const unsigned int vin2_data_pins[] = {
/* B */
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
/* G */
+ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
/* R */
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
};
-static const unsigned int vin2_data18_mux[] = {
+static const unsigned int vin2_data_mux[] = {
/* B */
+ VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
/* G */
+ VI2_G0_MARK, VI2_G1_MARK,
VI2_G2_MARK, VI2_G3_MARK,
VI2_G4_MARK, VI2_G5_MARK,
VI2_G6_MARK, VI2_G7_MARK,
/* R */
+ VI2_R0_MARK, VI2_R1_MARK,
VI2_R2_MARK, VI2_R3_MARK,
VI2_R4_MARK, VI2_R5_MARK,
VI2_R6_MARK, VI2_R7_MARK,
};
-static const unsigned int vin2_g8_pins[] = {
- RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
+static const unsigned int vin2_data18_pins[] = {
+ /* B */
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ /* G */
RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ /* R */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
+ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
};
-static const unsigned int vin2_g8_mux[] = {
- VI2_G0_MARK, VI2_G1_MARK,
+static const unsigned int vin2_data18_mux[] = {
+ /* B */
+ VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
+ VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+ VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+ /* G */
VI2_G2_MARK, VI2_G3_MARK,
VI2_G4_MARK, VI2_G5_MARK,
VI2_G6_MARK, VI2_G7_MARK,
+ /* R */
+ VI2_R2_MARK, VI2_R3_MARK,
+ VI2_R4_MARK, VI2_R5_MARK,
+ VI2_R6_MARK, VI2_R7_MARK,
};
static const unsigned int vin2_sync_pins[] = {
RCAR_GP_PIN(1, 16), /* HSYNC */
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
SH_PFC_PIN_GROUP(intc_irq3),
- SH_PFC_PIN_GROUP(mmc0_data1),
- SH_PFC_PIN_GROUP(mmc0_data4),
- SH_PFC_PIN_GROUP(mmc0_data8),
+ BUS_DATA_PIN_GROUP(mmc0_data, 1),
+ BUS_DATA_PIN_GROUP(mmc0_data, 4),
+ BUS_DATA_PIN_GROUP(mmc0_data, 8),
SH_PFC_PIN_GROUP(mmc0_ctrl),
- SH_PFC_PIN_GROUP(mmc1_data1),
- SH_PFC_PIN_GROUP(mmc1_data4),
- SH_PFC_PIN_GROUP(mmc1_data8),
+ BUS_DATA_PIN_GROUP(mmc1_data, 1),
+ BUS_DATA_PIN_GROUP(mmc1_data, 4),
+ BUS_DATA_PIN_GROUP(mmc1_data, 8),
SH_PFC_PIN_GROUP(mmc1_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(qspi_ctrl),
- SH_PFC_PIN_GROUP(qspi_data2),
- SH_PFC_PIN_GROUP(qspi_data4),
+ BUS_DATA_PIN_GROUP(qspi_data, 2),
+ BUS_DATA_PIN_GROUP(qspi_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(scifb2_data_c),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd),
SH_PFC_PIN_GROUP(sdhi2_wp),
- SH_PFC_PIN_GROUP(sdhi3_data1),
- SH_PFC_PIN_GROUP(sdhi3_data4),
+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
SH_PFC_PIN_GROUP(tpu0_to2),
SH_PFC_PIN_GROUP(tpu0_to3),
SH_PFC_PIN_GROUP(usb0),
- SH_PFC_PIN_GROUP(usb0_ovc_vbus),
+ SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
SH_PFC_PIN_GROUP(usb1),
- SH_PFC_PIN_GROUP(usb1_pwen),
+ SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
SH_PFC_PIN_GROUP(usb2),
- VIN_DATA_PIN_GROUP(vin0_data, 24),
- VIN_DATA_PIN_GROUP(vin0_data, 20),
+ BUS_DATA_PIN_GROUP(vin0_data, 24),
+ BUS_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
- VIN_DATA_PIN_GROUP(vin0_data, 16),
- VIN_DATA_PIN_GROUP(vin0_data, 12),
- VIN_DATA_PIN_GROUP(vin0_data, 10),
- VIN_DATA_PIN_GROUP(vin0_data, 8),
- VIN_DATA_PIN_GROUP(vin0_data, 4),
+ BUS_DATA_PIN_GROUP(vin0_data, 16),
+ BUS_DATA_PIN_GROUP(vin0_data, 12),
+ BUS_DATA_PIN_GROUP(vin0_data, 10),
+ BUS_DATA_PIN_GROUP(vin0_data, 8),
+ BUS_DATA_PIN_GROUP(vin0_data, 4),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
- VIN_DATA_PIN_GROUP(vin1_data, 24),
- VIN_DATA_PIN_GROUP(vin1_data, 20),
+ BUS_DATA_PIN_GROUP(vin1_data, 24),
+ BUS_DATA_PIN_GROUP(vin1_data, 20),
SH_PFC_PIN_GROUP(vin1_data18),
- VIN_DATA_PIN_GROUP(vin1_data, 16),
- VIN_DATA_PIN_GROUP(vin1_data, 12),
- VIN_DATA_PIN_GROUP(vin1_data, 10),
- VIN_DATA_PIN_GROUP(vin1_data, 8),
- VIN_DATA_PIN_GROUP(vin1_data, 4),
- VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
- VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 16),
+ BUS_DATA_PIN_GROUP(vin1_data, 12),
+ BUS_DATA_PIN_GROUP(vin1_data, 10),
+ BUS_DATA_PIN_GROUP(vin1_data, 8),
+ BUS_DATA_PIN_GROUP(vin1_data, 4),
+ BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
- VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
- VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
- VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
- VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
- VIN_DATA_PIN_GROUP(vin1_data, 4, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
+ BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_sync_b),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb_b),
SH_PFC_PIN_GROUP(vin1_clk),
SH_PFC_PIN_GROUP(vin1_clk_b),
- VIN_DATA_PIN_GROUP(vin2_data, 24),
+ BUS_DATA_PIN_GROUP(vin2_data, 24),
SH_PFC_PIN_GROUP(vin2_data18),
- VIN_DATA_PIN_GROUP(vin2_data, 16),
- VIN_DATA_PIN_GROUP(vin2_data, 8),
- VIN_DATA_PIN_GROUP(vin2_data, 4),
- SH_PFC_PIN_GROUP(vin2_g8),
+ BUS_DATA_PIN_GROUP(vin2_data, 16),
+ BUS_DATA_PIN_GROUP(vin2_data, 8),
+ BUS_DATA_PIN_GROUP(vin2_data, 4),
+ SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
SH_PFC_PIN_GROUP(vin2_sync),
SH_PFC_PIN_GROUP(vin2_field),
SH_PFC_PIN_GROUP(vin2_clkenb),
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
- SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
+ SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(du2),
GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
+ GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
GROUP(
- /* IP0_31 [1] */
- 0, 0,
+ /* IP0_31 [1] RESERVED */
/* IP0_30_27 [4] */
FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
- GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
+ GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
GROUP(
- /* IP1_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP1_31_30 [2] RESERVED */
/* IP1_29_28 [2] */
FN_A1, FN_PWM4, 0, 0,
/* IP1_27_26 [2] */
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
- GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
+ GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP2_31_29 [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP2_31_29 [3] RESERVED */
/* IP2_28_26 [3] */
FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
- GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
- /* IP4_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP4_31_30 [2] RESERVED */
/* IP4_29_27 [3] */
FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
- GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
+ GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
GROUP(
- /* IP5_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP5_31_30 [2] RESERVED */
/* IP5_29_27 [3] */
FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
/* IP5_26_24 [3] */
- FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
- FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
- FN_MSIOF0_SCK_B, 0,
+ FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
+ FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
/* IP5_23_21 [3] */
FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
/* IP5_17_15 [3] */
FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
- FN_INTC_IRQ4_N, 0, 0,
+ 0, 0, 0,
/* IP5_14_13 [2] */
FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
/* IP5_12_10 [3] */
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
FN_I2C2_SCL_E, 0,
/* IP6_13_11 [3] */
- FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
- FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+ FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
+ FN_MSIOF0_RXD_B, 0, 0,
/* IP6_10_9 [2] */
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
/* IP6_8_6 [3] */
- FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
- FN_SSI_SDATA8_C, 0, 0, 0,
+ FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
/* IP6_5_3 [3] */
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
+ FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
+ FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
+ GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
GROUP(
- /* IP7_31 [1] */
- 0, 0,
+ /* IP7_31 [1] RESERVED */
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
/* IP7_28_27 [2] */
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
+ GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2),
GROUP(
- /* IP8_31 [1] */
- 0, 0,
+ /* IP8_31 [1] RESERVED */
/* IP8_30_29 [2] */
FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
/* IP8_28 [1] */
FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
+ GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
GROUP(
- /* IP10_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP10_31_30 [2] RESERVED */
/* IP10_29_26 [4] */
FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
+ GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(
- /* IP12_31 [1] */
- 0, 0,
+ /* IP12_31 [1] RESERVED */
/* IP12_30_28 [3] */
FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
+ GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
GROUP(
- /* IP13_31 [1] */
- 0, 0,
+ /* IP13_31 [1] RESERVED */
/* IP13_30_29 [2] */
FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
/* IP13_28_26 [3] */
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
+ GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
GROUP(
- /* IP14_30 [1] */
- 0, 0,
+ /* IP14_30 [1] RESERVED */
/* IP14_30_28 [3] */
FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
+ GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
- /* IP15_31_30 [2] */
- 0, 0, 0, 0,
+ /* IP15_31_30 [2] RESERVED */
/* IP15_29_28 [2] */
FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
/* IP15_27_26 [2] */
FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
+ GROUP(-24, 1, 1, 3, 3),
GROUP(
- /* IP16_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_11_8 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP16_31_8 [24] RESERVED */
/* IP16_7 [1] */
FN_USB1_OVC, FN_TCLK1_B,
/* IP16_6 [1] */
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
- 1, 1, 1, 2, 1, 1, 2, 1, 1),
+ 1, 1, 1, 2, -1, 1, 2, 1, 1),
GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
/* SEL_TSIF1 [2] */
FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
/* RESERVED [1] */
- 0, 0,
/* SEL_LBS [1] */
FN_SEL_LBS_0, FN_SEL_LBS_1,
/* SEL_TSIF0 [2] */
FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
- 3, 3, 2, 3, 2, 2),
+ GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
+ 3, 3, 2, -3, 2, 2),
GROUP(
/* RESERVED [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
/* SEL_HSCIF1 [1] */
/* SEL_CAN1 [1] */
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
/* RESERVED [2] */
- 0, 0, 0, 0,
/* SEL_SCIF2 [1] */
FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
/* SEL_ADI [1] */
/* SEL_GPS [2] */
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
/* RESERVED [3] */
- 0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
+ GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- /* RESERVED [2] */
- 0, 0, 0, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
+ /* RESERVED [12] */
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* RESERVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED [2] */
- 0, 0, 0, 0,
+ /* RESERVED [6] */
/* SEL_IIC2 [3] */
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
FN_SEL_IIC2_4, 0, 0, 0,
{ },
};
-static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
return -EINVAL;
return 31 - (pin & 0x1f);
}
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+ { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(0, 16), /* A0 */
+ [ 1] = RCAR_GP_PIN(0, 17), /* A1 */
+ [ 2] = RCAR_GP_PIN(0, 18), /* A2 */
+ [ 3] = RCAR_GP_PIN(0, 19), /* A3 */
+ [ 4] = RCAR_GP_PIN(0, 20), /* A4 */
+ [ 5] = RCAR_GP_PIN(0, 21), /* A5 */
+ [ 6] = RCAR_GP_PIN(0, 22), /* A6 */
+ [ 7] = RCAR_GP_PIN(0, 23), /* A7 */
+ [ 8] = RCAR_GP_PIN(0, 24), /* A8 */
+ [ 9] = RCAR_GP_PIN(0, 25), /* A9 */
+ [10] = RCAR_GP_PIN(0, 26), /* A10 */
+ [11] = RCAR_GP_PIN(0, 27), /* A11 */
+ [12] = RCAR_GP_PIN(0, 28), /* A12 */
+ [13] = RCAR_GP_PIN(0, 29), /* A13 */
+ [14] = RCAR_GP_PIN(0, 30), /* A14 */
+ [15] = RCAR_GP_PIN(0, 31), /* A15 */
+ [16] = RCAR_GP_PIN(1, 0), /* A16 */
+ [17] = RCAR_GP_PIN(1, 1), /* A17 */
+ [18] = RCAR_GP_PIN(1, 2), /* A18 */
+ [19] = RCAR_GP_PIN(1, 3), /* A19 */
+ [20] = RCAR_GP_PIN(1, 4), /* A20 */
+ [21] = RCAR_GP_PIN(1, 5), /* A21 */
+ [22] = RCAR_GP_PIN(1, 6), /* A22 */
+ [23] = RCAR_GP_PIN(1, 7), /* A23 */
+ [24] = RCAR_GP_PIN(1, 8), /* A24 */
+ [25] = RCAR_GP_PIN(1, 9), /* A25 */
+ [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
+ [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
+ [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
+ [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
+ [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
+ [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
+ } },
+ { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
+ /* PUPR1 pull-up pins */
+ [ 0] = RCAR_GP_PIN(1, 18), /* BS# */
+ [ 1] = RCAR_GP_PIN(1, 19), /* RD# */
+ [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */
+ [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */
+ [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */
+ [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
+ [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */
+ [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */
+ [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */
+ [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
+ [10] = PIN_TRST_N, /* TRST# */
+ [11] = PIN_TCK, /* TCK */
+ [12] = PIN_TMS, /* TMS */
+ [13] = PIN_TDI, /* TDI */
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = RCAR_GP_PIN(0, 0), /* D0 */
+ [17] = RCAR_GP_PIN(0, 1), /* D1 */
+ [18] = RCAR_GP_PIN(0, 2), /* D2 */
+ [19] = RCAR_GP_PIN(0, 3), /* D3 */
+ [20] = RCAR_GP_PIN(0, 4), /* D4 */
+ [21] = RCAR_GP_PIN(0, 5), /* D5 */
+ [22] = RCAR_GP_PIN(0, 6), /* D6 */
+ [23] = RCAR_GP_PIN(0, 7), /* D7 */
+ [24] = RCAR_GP_PIN(0, 8), /* D8 */
+ [25] = RCAR_GP_PIN(0, 9), /* D9 */
+ [26] = RCAR_GP_PIN(0, 10), /* D10 */
+ [27] = RCAR_GP_PIN(0, 11), /* D11 */
+ [28] = RCAR_GP_PIN(0, 12), /* D12 */
+ [29] = RCAR_GP_PIN(0, 13), /* D13 */
+ [30] = RCAR_GP_PIN(0, 14), /* D14 */
+ [31] = RCAR_GP_PIN(0, 15), /* D15 */
+ } },
+ { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
+ /* PUPR1 pull-down pins */
+ [ 0] = SH_PFC_PIN_NONE,
+ [ 1] = SH_PFC_PIN_NONE,
+ [ 2] = SH_PFC_PIN_NONE,
+ [ 3] = SH_PFC_PIN_NONE,
+ [ 4] = SH_PFC_PIN_NONE,
+ [ 5] = SH_PFC_PIN_NONE,
+ [ 6] = SH_PFC_PIN_NONE,
+ [ 7] = SH_PFC_PIN_NONE,
+ [ 8] = SH_PFC_PIN_NONE,
+ [ 9] = SH_PFC_PIN_NONE,
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
+ [ 1] = SH_PFC_PIN_NONE,
+ [ 2] = SH_PFC_PIN_NONE,
+ [ 3] = SH_PFC_PIN_NONE,
+ [ 4] = SH_PFC_PIN_NONE,
+ [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
+ [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */
+ [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */
+ [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */
+ [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */
+ [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */
+ [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */
+ [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */
+ [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */
+ [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */
+ [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */
+ [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */
+ [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */
+ [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */
+ [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */
+ [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */
+ [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */
+ [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */
+ [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
+ [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */
+ [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */
+ [30] = SH_PFC_PIN_NONE,
+ [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */
+ } },
+ { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
+ [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
+ [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
+ [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
+ [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
+ [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
+ [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */
+ [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */
+ [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */
+ [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */
+ [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */
+ [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */
+ [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */
+ [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */
+ [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */
+ [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */
+ [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */
+ [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */
+ [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */
+ [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */
+ [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */
+ [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */
+ [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */
+ [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */
+ [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */
+ [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */
+ [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */
+ [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
+ [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */
+ [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */
+ [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */
+ [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */
+ } },
+ { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
+ [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */
+ [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */
+ [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */
+ [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */
+ [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */
+ [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */
+ [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */
+ [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */
+ [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */
+ [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */
+ [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */
+ [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */
+ [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */
+ [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */
+ [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */
+ [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */
+ [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */
+ [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */
+ [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */
+ [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */
+ [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */
+ [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */
+ [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */
+ [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */
+ [25] = RCAR_GP_PIN(1, 25), /* DACK0 */
+ [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */
+ [27] = RCAR_GP_PIN(1, 27), /* DACK1 */
+ [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */
+ [29] = RCAR_GP_PIN(1, 29), /* DACK2 */
+ [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */
+ [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */
+ } },
+ { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
+ [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */
+ [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */
+ [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */
+ [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */
+ [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
+ [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */
+ [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */
+ [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */
+ [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */
+ [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */
+ [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */
+ [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */
+ [13] = RCAR_GP_PIN(5, 8), /* HRX0 */
+ [14] = RCAR_GP_PIN(5, 9), /* HTX0 */
+ [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */
+ [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */
+ [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */
+ [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
+ [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
+ [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */
+ [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */
+ [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */
+ [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */
+ [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */
+ [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */
+ [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */
+ [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */
+ [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */
+ [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */
+ [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */
+ [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */
+ } },
+ { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
+ [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
+ [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */
+ [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */
+ [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */
+ [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */
+ [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */
+ [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */
+ [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */
+ [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */
+ [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */
+ [10] = SH_PFC_PIN_NONE,
+ [11] = SH_PFC_PIN_NONE,
+ [12] = SH_PFC_PIN_NONE,
+ [13] = SH_PFC_PIN_NONE,
+ [14] = SH_PFC_PIN_NONE,
+ [15] = SH_PFC_PIN_NONE,
+ [16] = SH_PFC_PIN_NONE,
+ [17] = SH_PFC_PIN_NONE,
+ [18] = SH_PFC_PIN_NONE,
+ [19] = SH_PFC_PIN_NONE,
+ [20] = SH_PFC_PIN_NONE,
+ [21] = SH_PFC_PIN_NONE,
+ [22] = SH_PFC_PIN_NONE,
+ [23] = SH_PFC_PIN_NONE,
+ [24] = SH_PFC_PIN_NONE,
+ [25] = SH_PFC_PIN_NONE,
+ [26] = SH_PFC_PIN_NONE,
+ [27] = SH_PFC_PIN_NONE,
+ [28] = SH_PFC_PIN_NONE,
+ [29] = SH_PFC_PIN_NONE,
+ [30] = SH_PFC_PIN_NONE,
+ [31] = SH_PFC_PIN_NONE,
+ } },
+ { /* sentinel */ }
+};
+
static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
{
/* Initialize TDSEL on old revisions */
return 0;
}
-static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
.init = r8a7790_pinmux_soc_init,
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
+};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A7742
+const struct sh_pfc_soc_info r8a7742_pinmux_info = {
+ .name = "r8a77420_pfc",
+ .ops = &r8a7790_pfc_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
+
+ .cfg_regs = pinmux_config_regs,
+ .bias_regs = pinmux_bias_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
- .ops = &r8a7790_pinmux_ops,
+ .ops = &r8a7790_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
+ .bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / platform / kernel / u-boot.git / commitdiff