drm/amd/display: Move dpp reg access from hwss to dpp module.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index c9a45d5..b3cd7ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -140,10 +140,6 @@
        BL_REG_LIST()
 
 #define HWSEQ_DCN_REG_LIST()\
-       SRII(DPP_CONTROL, DPP_TOP, 0), \
-       SRII(DPP_CONTROL, DPP_TOP, 1), \
-       SRII(DPP_CONTROL, DPP_TOP, 2), \
-       SRII(DPP_CONTROL, DPP_TOP, 3), \
        SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
        SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
        SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
@@ -252,7 +248,6 @@ struct dce_hwseq_registers {
        uint32_t DCHUB_AGP_BOT;
        uint32_t DCHUB_AGP_TOP;
 
-       uint32_t DPP_CONTROL[4];
        uint32_t OPP_PIPE_CONTROL[4];
        uint32_t REFCLK_CNTL;
        uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
@@ -423,7 +418,6 @@ struct dce_hwseq_registers {
 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
        HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
        HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
-       HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
        HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
        HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
@@ -445,7 +439,6 @@ struct dce_hwseq_registers {
        HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
        HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
        HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
-       HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \
        /* todo:  get these from GVM instead of reading registers ourselves */\
        HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
        HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
@@ -520,7 +513,6 @@ struct dce_hwseq_registers {
        type HUBP_VTG_SEL; \
        type HUBP_CLOCK_ENABLE; \
        type DPP_CLOCK_ENABLE; \
-       type DPPCLK_RATE_CONTROL; \
        type SDPIF_FB_TOP;\
        type SDPIF_FB_BASE;\
        type SDPIF_FB_OFFSET;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index f2a08b1..080c253 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -424,6 +424,26 @@ void dpp1_set_cursor_position(
 
 }
 
+void dpp1_dppclk_control(
+               struct dpp *dpp_base,
+               bool dppclk_div,
+               bool enable)
+{
+       struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
+       if (enable) {
+               if (dpp->tf_mask->DPPCLK_RATE_CONTROL) {
+                       REG_UPDATE_2(DPP_CONTROL,
+                               DPPCLK_RATE_CONTROL, dppclk_div,
+                               DPP_CLOCK_ENABLE, 1);
+               } else {
+                       ASSERT(dppclk_div == false);
+                       REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
+               }
+       } else
+               REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
+}
+
 static const struct dpp_funcs dcn10_dpp_funcs = {
                .dpp_reset = dpp_reset,
                .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
@@ -445,6 +465,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
                .dpp_full_bypass                = dpp1_full_bypass,
                .set_cursor_attributes = dpp1_set_cursor_attributes,
                .set_cursor_position = dpp1_set_cursor_position,
+               .dpp_dppclk_control = dpp1_dppclk_control,
 };
 
 static struct dpp_caps dcn10_dpp_cap = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index f56ee4d..ad6073a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -112,7 +112,8 @@
        SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
        SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
        SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
-       SRI(CURSOR0_COLOR1, CNVC_CUR, id)
+       SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
+       SRI(DPP_CONTROL, DPP_TOP, id)
 
 
 
@@ -306,7 +307,8 @@
        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
        TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
-       TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh)
+       TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
+       TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh)
 
 #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
        TF_REG_LIST_SH_MASK_DCN(mask_sh),\
@@ -410,7 +412,8 @@
        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
-       TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh)
+       TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+       TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
 
 #define TF_REG_FIELD_LIST(type) \
        type EXT_OVERSCAN_LEFT; \
@@ -1007,7 +1010,9 @@
        type CM_BYPASS; \
        type FORMAT_CONTROL__ALPHA_EN; \
        type CUR0_COLOR0; \
-       type CUR0_COLOR1;
+       type CUR0_COLOR1; \
+       type DPPCLK_RATE_CONTROL; \
+       type DPP_CLOCK_ENABLE;
 
 struct dcn_dpp_shift {
        TF_REG_FIELD_LIST(uint8_t)
@@ -1252,7 +1257,8 @@ struct dcn_dpp_mask {
        uint32_t CURSOR_CONTROL; \
        uint32_t CURSOR0_CONTROL; \
        uint32_t CURSOR0_COLOR0; \
-       uint32_t CURSOR0_COLOR1;
+       uint32_t CURSOR0_COLOR1; \
+       uint32_t DPP_CONTROL;
 
 struct dcn_dpp_registers {
        DPP_COMMON_REG_VARIABLE_LIST
@@ -1397,6 +1403,11 @@ void dpp1_cnv_setup (
 
 void dpp1_full_bypass(struct dpp *dpp_base);
 
+void dpp1_dppclk_control(
+               struct dpp *dpp_base,
+               bool dppclk_div,
+               bool enable);
+
 void dpp1_construct(struct dcn10_dpp *dpp1,
        struct dc_context *ctx,
        uint32_t inst,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4fedd7b..5431de7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -193,26 +193,6 @@ void dcn10_log_hw_state(struct dc *dc)
        DTN_INFO_END();
 }
 
-static void enable_dppclk(
-       struct dce_hwseq *hws,
-       uint8_t plane_id,
-       uint32_t requested_pix_clk,
-       bool dppclk_div)
-{
-       dm_logger_write(hws->ctx->logger, LOG_SURFACE,
-                       "dppclk_rate_control for pipe %d programed to %d\n",
-                       plane_id,
-                       dppclk_div);
-
-       if (hws->shifts->DPPCLK_RATE_CONTROL)
-               REG_UPDATE_2(DPP_CONTROL[plane_id],
-                       DPPCLK_RATE_CONTROL, dppclk_div,
-                       DPP_CLOCK_ENABLE, 1);
-       else
-               REG_UPDATE(DPP_CONTROL[plane_id],
-                       DPP_CLOCK_ENABLE, 1);
-}
-
 static void enable_power_gating_plane(
        struct dce_hwseq *hws,
        bool enable)
@@ -655,15 +635,14 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
        struct dce_hwseq *hws = dc->hwseq;
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
+       struct dpp *dpp = pipe_ctx->plane_res.dpp;
        int opp_id = hubp->opp_id;
-       int dpp_id = pipe_ctx->plane_res.dpp->inst;
 
        dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 
        hubp->funcs->hubp_clk_cntl(hubp, false);
 
-       REG_UPDATE(DPP_CONTROL[dpp_id],
-                       DPP_CLOCK_ENABLE, 0);
+       dpp->funcs->dpp_dppclk_control(dpp, false, false);
 
        if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
                REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
@@ -1688,11 +1667,11 @@ static void update_dchubp_dpp(
 
        /* depends on DML calculation, DPP clock value may change dynamically */
        if (plane_state->update_flags.bits.full_update) {
-               enable_dppclk(
-                       dc->hwseq,
-                       pipe_ctx->plane_res.dpp->inst,
-                       pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
-                       context->bw.dcn.calc_clk.dppclk_div);
+               dpp->funcs->dpp_dppclk_control(
+                               dpp,
+                               context->bw.dcn.calc_clk.dppclk_div,
+                               true);
+
                dc->current_state->bw.dcn.cur_clk.dppclk_div =
                                context->bw.dcn.calc_clk.dppclk_div;
                context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index d7b5bd2..819b749 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -33,7 +33,6 @@
 
 #define IPP_REG_LIST_DCN(id) \
        SRI(FORMAT_CONTROL, CNVC_CFG, id), \
-       SRI(DPP_CONTROL, DPP_TOP, id), \
        SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
        SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
        SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
@@ -130,7 +129,6 @@ struct dcn10_ipp_mask {
 };
 
 struct dcn10_ipp_registers {
-       uint32_t DPP_CONTROL;
        uint32_t CURSOR_SETTINS;
        uint32_t CURSOR_SETTINGS;
        uint32_t CNVC_SURFACE_PIXEL_FORMAT;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 25edbde..78abc16 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -131,6 +131,11 @@ struct dpp_funcs {
                        uint32_t width
                        );
 
+       void (*dpp_dppclk_control)(
+                       struct dpp *dpp_base,
+                       bool dppclk_div,
+                       bool enable);
+
 };