clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
<&clkgen JH7110_SPDIF_CLK_CORE>,
<&clkgen JH7110_AUDIO_ROOT>,
- <&clkgen JH7110_MCLK_INNER>;
+ <&clkgen JH7110_MCLK_INNER>,
+ <&mclk_ext>, <&clkgen JH7110_MCLK>;
clock-names = "spdif-apb", "spdif-core",
- "audroot", "mclk_inner";
+ "audroot", "mclk_inner",
+ "mclk_ext", "mclk";
resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
reset-names = "rst_apb";
interrupts = <84>;
return -EINVAL;
}
- ret = clk_set_rate(spdif->audio_root, audio_root);
- if (ret) {
- dev_err(dai->dev, "failed to set audio_root rate :%d\n", ret);
- return ret;
- }
- dev_dbg(dai->dev, "audio_root get rate:%ld\n",
- clk_get_rate(spdif->audio_root));
-
- ret = clk_set_rate(spdif->mclk_inner, mclk);
- if (ret) {
- dev_err(dai->dev, "failed to set mclk_inner rate :%d\n", ret);
- return ret;
- }
+ mclk = clk_get_rate(spdif->mclk_ext);
+ dev_dbg(dai->dev, "mclk_ext get rate:%d\n", mclk);
- mclk = clk_get_rate(spdif->mclk_inner);
- dev_dbg(dai->dev, "mclk_inner get rate:%d\n", mclk);
/* (FCLK)4096000/128=32000 */
tsamplerate = (mclk / 128 + rate / 2) / rate - 1;
if (tsamplerate < 3)
{ .id = "spdif-core" },
{ .id = "audroot" },
{ .id = "mclk_inner"},
+ { .id = "mclk_ext"},
+ { .id = "mclk"},
};
int ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks);
spdif->spdif_core = clks[1].clk;
spdif->audio_root = clks[2].clk;
spdif->mclk_inner = clks[3].clk;
+ spdif->mclk_ext = clks[4].clk;
+ spdif->mclk = clks[5].clk;
+
return ret;
}
dev_dbg(&pdev->dev, "spdif->spdif_apb = %lu\n", clk_get_rate(spdif->spdif_apb));
dev_dbg(&pdev->dev, "spdif->spdif_core = %lu\n", clk_get_rate(spdif->spdif_core));
+ ret = clk_set_parent(spdif->mclk, spdif->mclk_ext);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set parent for mclk to mclk_ext ret=%d\n", ret);
+ goto disable_core_clk;
+ }
+
ret = reset_control_deassert(spdif->rst_apb);
if (ret) {
dev_err(&pdev->dev, "failed to deassert apb\n");