def : WriteRes<WriteFVarBlend, [JFPU01]> {
let Latency = 2;
- let ResourceCycles = [2];
+ let ResourceCycles = [4];
+ let NumMicroOps = 3;
}
def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
let Latency = 7;
- let ResourceCycles = [1, 2];
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 3;
}
// Vector integer operations.
def : WriteRes<WriteVarBlend, [JFPU01]> {
let Latency = 2;
- let ResourceCycles = [2];
+ let ResourceCycles = [4];
+ let NumMicroOps = 3;
}
def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
let Latency = 7;
- let ResourceCycles = [1, 2];
+ let ResourceCycles = [1, 4];
+ let NumMicroOps = 3;
}
// FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2?
-def : WriteRes<WriteVarVecShift, [JFPU01]> {
- let Latency = 1;
- let ResourceCycles = [1];
-}
+def : WriteRes<WriteVarVecShift, [JFPU01]> {}
def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
let Latency = 6;
- let ResourceCycles = [1, 1];
+ let ResourceCycles = [1, 2];
}
def : WriteRes<WriteMPSAD, [JFPU0]> {
// and ALU0 in the integer unit is occupied instead.
def WriteVTESTY: SchedWriteRes<[JFPU01, JFPU0]> {
let Latency = 4;
- let ResourceCycles = [4, 2];
+ let ResourceCycles = [2, 2];
+ let NumMicroOps = 3;
}
def : InstRW<[WriteVTESTY], (instregex "VTESTP(S|D)Yrr")>;
def : InstRW<[WriteVTESTY], (instregex "VPTESTYrr")>;
def WriteVTESTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPU0]> {
let Latency = 9;
- let ResourceCycles = [1, 4, 2];
+ let ResourceCycles = [1, 2, 2];
+ let NumMicroOps = 3;
}
def : InstRW<[WriteVTESTYLd], (instregex "VTESTP(S|D)Yrm")>;
def : InstRW<[WriteVTESTYLd], (instregex "VPTESTYrm")>;
+def WriteVTEST: SchedWriteRes<[JFPU0]> {
+ let Latency = 3;
+}
+def : InstRW<[WriteVTEST], (instregex "VTESTP(S|D)rr")>;
+def : InstRW<[WriteVTEST], (instregex "VPTESTrr")>;
+
+def WriteVTESTLd: SchedWriteRes<[JLAGU, JFPU0]> {
+ let Latency = 8;
+}
+def : InstRW<[WriteVTESTLd], (instregex "VTESTP(S|D)rm")>;
+def : InstRW<[WriteVTESTLd], (instregex "VPTESTrm")>;
+
def WriteVSQRTYPD: SchedWriteRes<[JFPU1]> {
let Latency = 54;
let ResourceCycles = [54];
; BTVER2-LABEL: test_testpd:
; BTVER2: # BB#0:
; BTVER2-NEXT: xorl %eax, %eax # sched: [1:0.50]
-; BTVER2-NEXT: vtestpd %xmm1, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vtestpd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: setb %al # sched: [1:0.50]
-; BTVER2-NEXT: vtestpd (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vtestpd (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: adcl $0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_testpd_ymm:
; BTVER2: # BB#0:
; BTVER2-NEXT: xorl %eax, %eax # sched: [1:0.50]
-; BTVER2-NEXT: vtestpd %ymm1, %ymm0 # sched: [4:3.00]
+; BTVER2-NEXT: vtestpd %ymm1, %ymm0 # sched: [4:2.00]
; BTVER2-NEXT: setb %al # sched: [1:0.50]
-; BTVER2-NEXT: vtestpd (%rdi), %ymm0 # sched: [9:3.00]
+; BTVER2-NEXT: vtestpd (%rdi), %ymm0 # sched: [9:2.00]
; BTVER2-NEXT: adcl $0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_testps:
; BTVER2: # BB#0:
; BTVER2-NEXT: xorl %eax, %eax # sched: [1:0.50]
-; BTVER2-NEXT: vtestps %xmm1, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vtestps %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: setb %al # sched: [1:0.50]
-; BTVER2-NEXT: vtestps (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vtestps (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: adcl $0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_testps_ymm:
; BTVER2: # BB#0:
; BTVER2-NEXT: xorl %eax, %eax # sched: [1:0.50]
-; BTVER2-NEXT: vtestps %ymm1, %ymm0 # sched: [4:3.00]
+; BTVER2-NEXT: vtestps %ymm1, %ymm0 # sched: [4:2.00]
; BTVER2-NEXT: setb %al # sched: [1:0.50]
-; BTVER2-NEXT: vtestps (%rdi), %ymm0 # sched: [9:3.00]
+; BTVER2-NEXT: vtestps (%rdi), %ymm0 # sched: [9:2.00]
; BTVER2-NEXT: adcl $0, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
;
; BTVER2-LABEL: test_blendvpd:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; BTVER2-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vblendvpd %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_blendvpd:
;
; BTVER2-LABEL: test_blendvps:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; BTVER2-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vblendvps %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_blendvps:
;
; BTVER2-LABEL: test_pblendvb:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
-; BTVER2-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; BTVER2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 # sched: [2:2.00]
+; BTVER2-NEXT: vpblendvb %xmm2, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pblendvb:
;
; BTVER2-LABEL: test_ptest:
; BTVER2: # BB#0:
-; BTVER2-NEXT: vptest %xmm1, %xmm0 # sched: [1:0.50]
+; BTVER2-NEXT: vptest %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: setb %al # sched: [1:0.50]
-; BTVER2-NEXT: vptest (%rdi), %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT: vptest (%rdi), %xmm0 # sched: [8:1.00]
; BTVER2-NEXT: setb %cl # sched: [1:0.50]
; BTVER2-NEXT: andb %al, %cl # sched: [1:0.50]
; BTVER2-NEXT: movzbl %cl, %eax # sched: [1:0.50]