net: sh-eth: Add control for padding size of packet descriptor

sh-eth can change the alignment size of a packet descriptor according to BUS
size. This patch adds this function.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 4cfd1e5..c038929 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -238,15 +238,17 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
         * Allocate rx data buffers. They must be 32 bytes aligned  and in
         * P2 area
         */
-       port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
+       port_info->rx_buf_malloc = malloc(
+               NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
        if (!port_info->rx_buf_malloc) {
                printf(SHETHER_NAME ": malloc failed\n");
                ret = -ENOMEM;
                goto err_buf_malloc;
        }
 
-       tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
-                         ~(32 - 1));
+       tmp_addr = (u32)(((int)port_info->rx_buf_malloc
+                         + (RX_BUF_ALIGNE_SIZE - 1)) &
+                         ~(RX_BUF_ALIGNE_SIZE - 1));
        port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
 
        /* Initialize all descriptors */
@@ -352,8 +354,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
        struct phy_device *phy;
 
        /* Configure e-dmac registers */
-       sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
-                    EDMR);
+       sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
+                       (EMDR_DESC | EDMR_EL), EDMR);
+
        sh_eth_write(eth, 0, EESIPR);
        sh_eth_write(eth, 0, TRSCER);
        sh_eth_write(eth, 0, TFTR);

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e..35a1eee 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
 #define ADDR_TO_P2(addr)       (addr)
 #endif /* defined(CONFIG_SH) */
 
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
 /* Number of supported ports */
 #define MAX_PORT_NUM   2
 
@@ -45,15 +50,16 @@
 
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING                4
-#define TX_DESC_SIZE           (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE   (12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
        volatile u32 td0;
        u32 td1;
        u32 td2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 /* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@ struct tx_desc_s {
 
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING                4
+#define RX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
 #define RX_DESC_SIZE           (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE     (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
 /* Rx descriptor. We always use 4 bytes of padding */
 struct rx_desc_s {
        volatile u32 rd0;
        volatile u32 rd1;
        u32 rd2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 struct sh_eth_info {
@@ -320,6 +329,14 @@ enum DMAC_M_BIT {
 #endif
 };
 
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
 /* RFLR */
 #define RFLR_RFL_MIN   0x05EE  /* Recv Frame length 1518 byte */