net: hns3: Use decimal for bit offset macros

Using hex for bit offsets is inconsistent with the rest
of the file. Change them to decimal.

Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 940c159..219ffc7 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -579,13 +579,13 @@ enum hclge_mac_vlan_tbl_opcode {
        HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 };
 
-#define HCLGE_MAC_VLAN_BIT0_EN_B       0x0
-#define HCLGE_MAC_VLAN_BIT1_EN_B       0x1
-#define HCLGE_MAC_EPORT_SW_EN_B                0xc
-#define HCLGE_MAC_EPORT_TYPE_B         0xb
-#define HCLGE_MAC_EPORT_VFID_S         0x3
+#define HCLGE_MAC_VLAN_BIT0_EN_B       0
+#define HCLGE_MAC_VLAN_BIT1_EN_B       1
+#define HCLGE_MAC_EPORT_SW_EN_B                12
+#define HCLGE_MAC_EPORT_TYPE_B         11
+#define HCLGE_MAC_EPORT_VFID_S         3
 #define HCLGE_MAC_EPORT_VFID_M         GENMASK(10, 3)
-#define HCLGE_MAC_EPORT_PFID_S         0x0
+#define HCLGE_MAC_EPORT_PFID_S         0
 #define HCLGE_MAC_EPORT_PFID_M         GENMASK(2, 0)
 struct hclge_mac_vlan_tbl_entry_cmd {
        u8      flags;
@@ -601,7 +601,7 @@ struct hclge_mac_vlan_tbl_entry_cmd {
        u8      rsv2[6];
 };
 
-#define HCLGE_VLAN_MASK_EN_B           0x0
+#define HCLGE_VLAN_MASK_EN_B           0
 struct hclge_mac_vlan_mask_entry_cmd {
        u8 rsv0[2];
        u8 vlan_mask;
@@ -632,23 +632,23 @@ struct hclge_mac_mgr_tbl_entry_cmd {
        u8      rsv3[2];
 };
 
-#define HCLGE_CFG_MTA_MAC_SEL_S                0x0
+#define HCLGE_CFG_MTA_MAC_SEL_S                0
 #define HCLGE_CFG_MTA_MAC_SEL_M                GENMASK(1, 0)
-#define HCLGE_CFG_MTA_MAC_EN_B         0x7
+#define HCLGE_CFG_MTA_MAC_EN_B         7
 struct hclge_mta_filter_mode_cmd {
        u8      dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
        u8      rsv[23];
 };
 
-#define HCLGE_CFG_FUNC_MTA_ACCEPT_B    0x0
+#define HCLGE_CFG_FUNC_MTA_ACCEPT_B    0
 struct hclge_cfg_func_mta_filter_cmd {
        u8      accept; /* Only used lowest 1 bit */
        u8      function_id;
        u8      rsv[22];
 };
 
-#define HCLGE_CFG_MTA_ITEM_ACCEPT_B    0x0
-#define HCLGE_CFG_MTA_ITEM_IDX_S       0x0
+#define HCLGE_CFG_MTA_ITEM_ACCEPT_B    0
+#define HCLGE_CFG_MTA_ITEM_IDX_S       0
 #define HCLGE_CFG_MTA_ITEM_IDX_M       GENMASK(11, 0)
 struct hclge_cfg_func_mta_item_cmd {
        __le16  item_idx; /* Only used lowest 12 bit */

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index b84a140..aeae1ba 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -91,8 +91,8 @@
 #define HCLGE_MISC_RESET_STS_REG       0x20700
 #define HCLGE_MISC_VECTOR_INT_STS      0x20800
 #define HCLGE_GLOBAL_RESET_REG         0x20A00
-#define HCLGE_GLOBAL_RESET_BIT         0x0
-#define HCLGE_CORE_RESET_BIT           0x1
+#define HCLGE_GLOBAL_RESET_BIT         0
+#define HCLGE_CORE_RESET_BIT           1
 #define HCLGE_FUN_RST_ING              0x20C00
 #define HCLGE_FUN_RST_ING_B            0