Use codespell to fix lots of typos over frontends.
Manually verified to avoid false-positives.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* SECAM->PAL (typically it does not work
* due to genlock: when decoder is in SECAM
* and encoder in in PAL the subcarrier can
- * not be syncronized with horizontal
+ * not be synchronized with horizontal
* quency) */
adv7175_write_block(sd, init_pal, sizeof(init_pal));
if (encoder->input == 0)
io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
io_write(sd, 0x01, 0x00); /* Program SDP mode */
- afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
- afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
- afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
- afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
- afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
+ afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
+ afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
+ afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
+ afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
+ afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
io_write(sd, 0x15, 0xBA); /* Enable outputs */
0x0e, 0xb4, /* 0x0e Chroma Gain (V) msb */
0x0f, 0x00, /* 0x0f Hue control */
0x12, 0x04, /* 0x12 Output Format */
- 0x13, 0x20, /* 0x13 Vertial Scaling msb 0x00
+ 0x13, 0x20, /* 0x13 Vertical Scaling msb 0x00
chroma comb OFF, line drop scaling, interlace scaling
BUG? Why does turning the chroma comb on fuck up color?
Bug in the bt819 stepping on my board?
*/
- 0x14, 0x00, /* 0x14 Vertial Scaling lsb */
+ 0x14, 0x00, /* 0x14 Vertical Scaling lsb */
0x16, 0x07, /* 0x16 Video Timing Polarity
ACTIVE=active low
FIELD: high=odd,
* @is_initialized: whether we have already loaded firmware into the chip
* and initialized it
* @vbi_regs_offset: offset of vbi regs
- * @fw_wait: wait queue to wake an initalization function up when
+ * @fw_wait: wait queue to wake an initialization function up when
* firmware loading (on a separate workqueue) finishes
* @fw_work: a work that actually loads the firmware on a separate
* workqueue
ror = stats & STATS_ROR; /* Rx FIFO Over Run */
tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
- rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
+ rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
}
if (v) {
- /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
+ /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
*handled = true;
{ ET8EK8_REG_8BIT, 0x1258, 0x00 },
/* From parallel out to serial out */
{ ET8EK8_REG_8BIT, 0x125D, 0x88 },
- /* From w/ embeded data to w/o embeded data */
+ /* From w/ embedded data to w/o embedded data */
{ ET8EK8_REG_8BIT, 0x125E, 0xC0 },
/* CCP2 out is from STOP to ACTIVE */
{ ET8EK8_REG_8BIT, 0x1263, 0x98 },
/* Moire reduction */
{0x6957, 0x01},
- /* image enhancment */
+ /* image enhancement */
{0x6987, 0x17},
{0x698A, 0x03},
{0x698B, 0x03},
*/
static const struct reg_8 imx274_start_3[] = {
{0x30F4, 0x00},
- {0x3018, 0xA2}, /* XHS VHS OUTUPT */
+ {0x3018, 0xA2}, /* XHS VHS OUTPUT */
{IMX274_TABLE_END, 0x00}
};
/*
- * imx274 register configuration for stoping stream
+ * imx274 register configuration for stopping stream
*/
static const struct reg_8 imx274_stop[] = {
{IMX274_STANDBY_REG, 0x01},
* @regmap: reg. map for i2c
* @lock: muxtex for serial access.
* @led_mode: V4L2 LED mode
- * @ctrls_led: V4L2 contols
+ * @ctrls_led: V4L2 controls
* @subdev_led: V4L2 subdev
*/
struct lm3560_flash {
* @regmap: reg. map for i2c
* @lock: muxtex for serial access.
* @led_mode: V4L2 LED mode
- * @ctrls_led: V4L2 contols
+ * @ctrls_led: V4L2 controls
* @subdev_led: V4L2 subdev
* @mode_reg : mode register value
*/
*
* The I2C read operation of the M-5MOLS requires 2 messages. The first
* message sends the information about the command, command category, and total
- * message size. The second message is used to retrieve the data specifed in
+ * message size. The second message is used to retrieve the data specified in
* the first message
*
* 1st message 2nd message
* @reg: the I2C_REG() address of an 8-bit status register to check
* @value: expected status register value
* @mask: bit mask for the read status register value
- * @timeout: timeout in miliseconds, or -1 for default timeout
+ * @timeout: timeout in milliseconds, or -1 for default timeout
*
* The @reg register value is ORed with @mask before comparing with @value.
*
*
* FM-Mono
* should work. The stereo modes are backward compatible to FM-mono,
- * therefore FM-Mono should be allways available.
+ * therefore FM-Mono should be always available.
*
* FM-Stereo (B/G, used in germany)
* should work, with autodetect
mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
/*
- * Flicker Dectection registers.
+ * Flicker Detection registers.
* This section should be replaced whenever new timing file is
* generated. All the following registers need to be replaced.
* Following registers are generated from Register Wizard but user can
/*
* After trying the various combinations, reading various
- * documentations spreaded around the net, and from the various
+ * documentations spread around the net, and from the various
* feedback, the clock tree is probably as follows:
*
* +--------------+
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
*
- * Hardware specific bits initialy based on former work by Matt Callow
+ * Hardware specific bits initially based on former work by Matt Callow
* drivers/media/video/omap/sensor_ov6650.c
* Copyright (C) 2006 Matt Callow
*
/*
* Keep result to be used as tpf limit
- * for subseqent clock divider calculations
+ * for subsequent clock divider calculations
*/
priv->tpf.numerator = div;
priv->tpf.denominator = FRAME_RATE_MAX;
#define REG_BGAIN 0x01 /* blue gain */
#define REG_RGAIN 0x02 /* red gain */
#define REG_GGAIN 0x03 /* green gain */
-#define REG_REG04 0x04 /* analog setting, dont change*/
+#define REG_REG04 0x04 /* analog setting, don't change*/
#define REG_BAVG 0x05 /* b channel average */
#define REG_GAVG 0x06 /* g channel average */
#define REG_RAVG 0x07 /* r channel average */
* OV9650/OV9652 register definitions
*/
#define REG_GAIN 0x00 /* Gain control, AGC[7:0] */
-#define REG_BLUE 0x01 /* AWB - Blue chanel gain */
-#define REG_RED 0x02 /* AWB - Red chanel gain */
+#define REG_BLUE 0x01 /* AWB - Blue channel gain */
+#define REG_RED 0x02 /* AWB - Red channel gain */
#define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */
#define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */
#define REG_COM1 0x04
for (++i; i < S5C73M3_MAX_SUPPLIES; i++) {
int r = regulator_enable(state->supplies[i].consumer);
if (r < 0)
- v4l2_err(&state->oif_sd, "Failed to reenable %s: %d\n",
+ v4l2_err(&state->oif_sd, "Failed to re-enable %s: %d\n",
state->supplies[i].supply, r);
}
* @s5k6aa: pointer to &struct s5k6aa describing the device
* @preset: s5kaa preset to be applied
*
- * Configure output resolution and color fromat, pixel clock
+ * Configure output resolution and color format, pixel clock
* frequency range, device frame rate type and frame period range.
*/
static int s5k6aa_set_prev_config(struct s5k6aa *s5k6aa,
* exists. However, tests on a device labeled as:
* "GM7113C 1145" returned "10" on all 16 chip
* version (reg 0x00) reads. So, we need to also
- * accept at least verion 0. For now, let's just
+ * accept at least version 0. For now, let's just
* assume that a device that returns "0000" for
* the lower nibble is a gm7113c.
*/
if (i == count)
return;
- /* horizonal prescaling */
+ /* horizontal prescaling */
saa717x_write(sd, 0x60 + task_shift, vals[i].xpsc);
/* accumulation length */
saa717x_write(sd, 0x61 + task_shift, vals[i].xacl);
#define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */
/* HDCP_BCAPS bits */
-#define HDCP_HDMI BIT(7) /* HDCP suports HDMI (vs DVI only) */
+#define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */
#define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */
#define HDCP_READY BIT(5) /* set by repeater function */
#define HDCP_FAST BIT(4) /* Up to 400kHz */
The tda9840 is a stereo/dual sound processor with digital
identification. It can be found at address 0x84 on the i2c-bus.
- For detailed informations download the specifications directly
+ For detailed information download the specifications directly
from SGS Thomson at http://www.st.com
This program is free software; you can redistribute it and/or modify
It is cascadable, i.e. it can be found at the addresses
0x86 and 0x06 on the i2c-bus.
- For detailed informations download the specifications directly
+ For detailed information download the specifications directly
from SGS Thomson at http://www.st.com
This program is free software; you can redistribute it and/or modify
It is cascadable, i.e. it can be found at the addresses 0x98
and 0x9a on the i2c-bus.
- For detailed informations download the specifications directly
+ For detailed information download the specifications directly
from SGS Thomson at http://www.st.com
This program is free software; you can redistribute it and/or modify
#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
/* Unique to TDA9850: */
-/* lower 4 bits contol SAP noise threshold, over which SAP turns off
+/* lower 4 bits control SAP noise threshold, over which SAP turns off
* set to values of 0x00 through 0x0f for SAP1 through SAP16 */
/* Common to TDA9855 and TDA9850: */
#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
#define TDA985x_MONOSAP 2<<6 /* Selects Mono on left, SAP on right */
-#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
+#define TDA985x_STEREO 1<<6 /* Selects Stereo output, mono if not received */
#define TDA985x_MONO 0 /* Forces Mono output */
#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
};
/**
- * struct tvp514x_std_info - Structure to store standard informations
+ * struct tvp514x_std_info - Structure to store standard information
* @width: Line width in pixels
* @height:Number of active lines
* @video_std: Value to write in REG_VIDEO_STD register
projects / platform / kernel / linux-starfive.git / commitdiff