arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets

Add nodes for topckgen, infracfg and pericfg, providing various
clocks and resets and needed to support basic IPs of this SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 46f0e54..aff9a5b 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -6,7 +6,9 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mediatek,mt6795-clk.h>
 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
+#include <dt-bindings/reset/mediatek,mt6795-resets.h>
 
 / {
        compatible = "mediatek,mt6795";
@@ -192,6 +194,26 @@
                compatible = "simple-bus";
                ranges;
 
+               topckgen: syscon@10000000 {
+                       compatible = "mediatek,mt6795-topckgen", "syscon";
+                       reg = <0 0x10000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               infracfg: syscon@10001000 {
+                       compatible = "mediatek,mt6795-infracfg", "syscon";
+                       reg = <0 0x10001000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               pericfg: syscon@10003000 {
+                       compatible = "mediatek,mt6795-pericfg", "syscon";
+                       reg = <0 0x10003000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                pio: pinctrl@10005000 {
                        compatible = "mediatek,mt6795-pinctrl";
                        reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;