ss_phy->lane_cnt = phy->attrs.bus_width;
ss_phy->ufs_phy_state = CFG_PRE_INIT;
- if (ss_phy->drvdata->has_symbol_clk) {
+ if (ss_phy->has_symbol_clk) {
ret = samsung_ufs_phy_symbol_clk_init(ss_phy);
if (ret)
dev_err(ss_phy->dev, "failed to set ufs phy symbol clocks\n");
clk_disable_unprepare(ss_phy->ref_clk);
- if (ss_phy->drvdata->has_symbol_clk) {
+ if (ss_phy->has_symbol_clk) {
clk_disable_unprepare(ss_phy->tx0_symbol_clk);
clk_disable_unprepare(ss_phy->rx0_symbol_clk);
clk_disable_unprepare(ss_phy->rx1_symbol_clk);
drvdata = match->data;
phy->dev = dev;
- phy->drvdata = drvdata;
phy->cfgs = drvdata->cfgs;
- phy->isol = &drvdata->isol;
+ phy->has_symbol_clk = drvdata->has_symbol_clk;
+ memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
+
phy->lane_cnt = PHY_DEF_LANE_CNT;
phy_set_drvdata(gen_phy, phy);
u8 id;
};
+struct samsung_ufs_phy_pmu_isol {
+ u32 offset;
+ u32 mask;
+ u32 en;
+};
+
struct samsung_ufs_phy_drvdata {
const struct samsung_ufs_phy_cfg **cfgs;
- struct pmu_isol {
- u32 offset;
- u32 mask;
- u32 en;
- } isol;
+ struct samsung_ufs_phy_pmu_isol isol;
bool has_symbol_clk;
};
struct clk *rx1_symbol_clk;
const struct samsung_ufs_phy_drvdata *drvdata;
const struct samsung_ufs_phy_cfg * const *cfgs;
- const struct pmu_isol *isol;
+ struct samsung_ufs_phy_pmu_isol isol;
+ bool has_symbol_clk;
u8 lane_cnt;
int ufs_phy_state;
enum phy_mode mode;
static inline void samsung_ufs_phy_ctrl_isol(
struct samsung_ufs_phy *phy, u32 isol)
{
- regmap_update_bits(phy->reg_pmu, phy->isol->offset,
- phy->isol->mask, isol ? 0 : phy->isol->en);
+ regmap_update_bits(phy->reg_pmu, phy->isol.offset,
+ phy->isol.mask, isol ? 0 : phy->isol.en);
}
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;