if (cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable ||
cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
- cmd_buffer->state.emitted_graphics_pipeline->pa_sc_mode_cntl_1 != pipeline->pa_sc_mode_cntl_1 ||
+ cmd_buffer->state.emitted_graphics_pipeline->uses_out_of_order_rast != pipeline->uses_out_of_order_rast ||
+ cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment ||
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
+
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
}
static void
radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
{
- const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const struct radv_rendering_state *render = &cmd_buffer->state.render;
- unsigned pa_sc_mode_cntl_1 = pipeline->pa_sc_mode_cntl_1;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
unsigned db_render_control = cmd_buffer->state.db_render_control;
+ unsigned pa_sc_mode_cntl_1;
+
+ pa_sc_mode_cntl_1 =
+ S_028A4C_WALK_FENCE_ENABLE(1) | // TODO linear dst fixes
+ S_028A4C_WALK_FENCE_SIZE(pdevice->rad_info.num_tile_pipes == 2 ? 2 : 3) |
+ S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(cmd_buffer->state.uses_out_of_order_rast) |
+ S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
+ /* always 1: */
+ S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
+ S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
+ /* This should only be set when VRS surfaces aren't enabled on GFX11, otherwise the GPU might
+ * hang.
+ */
+ S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(pdevice->rad_info.gfx_level < GFX11 ||
+ !cmd_buffer->state.uses_vrs_attachment);
if (!d->sample_location.count)
radv_emit_default_sample_locations(cmd_buffer->cs, rasterization_samples);
cmd_buffer->state.rast_prim = graphics_pipeline->rast_prim;
cmd_buffer->state.ia_multi_vgt_param = graphics_pipeline->ia_multi_vgt_param;
+
+ cmd_buffer->state.uses_out_of_order_rast = graphics_pipeline->uses_out_of_order_rast;
+ cmd_buffer->state.uses_vrs_attachment = graphics_pipeline->uses_vrs_attachment;
break;
}
default:
const struct vk_graphics_pipeline_state *state,
unsigned rast_prim)
{
- const struct radv_physical_device *pdevice = device->physical_device;
struct radv_multisample_state *ms = &pipeline->ms;
- unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes;
- bool out_of_order_rast =
- state->rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD;
/* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
*
ms->min_sample_shading = state->ms->min_sample_shading;
}
- pipeline->pa_sc_mode_cntl_1 =
- S_028A4C_WALK_FENCE_ENABLE(1) | // TODO linear dst fixes
- S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
- S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
- S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
- /* always 1: */
- S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
- S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
- S_028A4C_FORCE_EOV_REZ_ENABLE(1);
-
- if (pdevice->rad_info.gfx_level < GFX11 ||
- !radv_pipeline_uses_vrs_attachment(pCreateInfo, state)) {
- /* This should only be set when VRS surfaces aren't enabled on GFX11, otherwise the GPU might
- * hang.
- */
- pipeline->pa_sc_mode_cntl_1 |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
- }
-
ms->uses_user_sample_locations = state->ms && state->ms->sample_locations_enable;
}
pipeline->force_vrs_per_vertex =
pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
pipeline->rast_prim = vgt_gs_out_prim_type;
+ pipeline->uses_out_of_order_rast =
+ state.rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD;
+ pipeline->uses_vrs_attachment = radv_pipeline_uses_vrs_attachment(pCreateInfo, &state);
pipeline->base.push_constant_size = pipeline_layout.push_constant_size;
pipeline->base.dynamic_offset_count = pipeline_layout.dynamic_offset_count;
uint8_t vtx_emit_num;
bool uses_drawid;
bool uses_baseinstance;
+
+ bool uses_out_of_order_rast;
+ bool uses_vrs_attachment;
};
struct radv_cmd_buffer_upload {
uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
uint32_t attrib_ends[MAX_VERTEX_ATTRIBS];
uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
- uint32_t pa_sc_mode_cntl_1;
uint32_t db_render_control;
/* Last pre-PS API stage */
/* Custom blend mode for internal operations. */
unsigned custom_blend_mode;
+ /* Whether the pipeline uses out-of-order rasterization. */
+ bool uses_out_of_order_rast;
+
+ /* Whether the pipeline uses a VRS attachment. */
+ bool uses_vrs_attachment;
+
/* For graphics pipeline library */
bool retain_shaders;
struct {