wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
wl->chip.id);
- wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT |
- WLCORE_QUIRK_LEGACY_NVS;
- wl->plt_fw_name = WL127X_PLT_FW_NAME;
+ /* clear the alignment quirk, since we don't support it */
+ wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
+
+ wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
wl->mr_fw_name = WL127X_FW_NAME_MULTI;
wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
wl->chip.id);
- wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT |
- WLCORE_QUIRK_LEGACY_NVS;
+ /* clear the alignment quirk, since we don't support it */
+ wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
+
+ wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
wl->plt_fw_name = WL127X_PLT_FW_NAME;
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
wl->mr_fw_name = WL127X_FW_NAME_MULTI;
if (wl->chip.id == CHIP_ID_1283_PG20) {
u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
- if (!(wl->quirks & WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT))
+ if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
/* Enable SDIO padding */
host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
* negligible, we use the same block size for all different
* chip types.
*/
- if (!wl1271_set_block_size(wl))
- wl->quirks |= WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT;
+ if (wl1271_set_block_size(wl))
+ wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
ret = wl->ops->identify_chip(wl);
if (ret < 0)
unsigned int wlcore_calc_packet_alignment(struct wl1271 *wl,
unsigned int packet_length)
{
- if (wl->quirks & WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT)
- return ALIGN(packet_length, WL1271_TX_ALIGN_TO);
- else
+ if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
return ALIGN(packet_length, WL12XX_BUS_BLOCK_SIZE);
+ else
+ return ALIGN(packet_length, WL1271_TX_ALIGN_TO);
}
EXPORT_SYMBOL(wlcore_calc_packet_alignment);
#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
/* wl127x and SPI don't support SDIO block size alignment */
-#define WLCORE_QUIRK_NO_BLOCKSIZE_ALIGNMENT BIT(2)
+#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
/* means aggregated Rx packets are aligned to a SDIO block */
#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)