Fix the remaining jitstress-isas-x86 failures (#37459)

* Ensure the right SIMD size is used for the AsVector256 AVX code

* Don't create GT_SIMD nodes if the baseline ISAs are not supported.

diff --git a/src/coreclr/src/jit/hwintrinsicxarch.cpp b/src/coreclr/src/jit/hwintrinsicxarch.cpp
index f1b7fa9..9cbd3e1 100644 (file)
--- a/src/coreclr/src/jit/hwintrinsicxarch.cpp
+++ b/src/coreclr/src/jit/hwintrinsicxarch.cpp
@@ -707,7 +707,7 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic        intrinsic,
                 else
                 {
                     assert(intrinsic == NI_Vector256_AsVector256);
-                    return impBaseIntrinsic(NI_Vector128_ToVector256, clsHnd, method, sig, baseType, retType, simdSize);
+                    return impBaseIntrinsic(NI_Vector128_ToVector256, clsHnd, method, sig, baseType, retType, 16);
                 }
             }
 

diff --git a/src/coreclr/src/jit/simd.cpp b/src/coreclr/src/jit/simd.cpp
index 3bd38ef..6b86f8c 100644 (file)
--- a/src/coreclr/src/jit/simd.cpp
+++ b/src/coreclr/src/jit/simd.cpp
@@ -1824,6 +1824,25 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE                opcode,
         return nullptr;
     }
 
+#if defined(TARGET_XARCH)
+    CORINFO_InstructionSet minimumIsa = InstructionSet_SSE2;
+#elif defined(TARGET_ARM64)
+    CORINFO_InstructionSet minimumIsa = InstructionSet_AdvSimd;
+#else
+#error Unsupported platform
+#endif // !TARGET_XARCH && !TARGET_ARM64
+
+    if (!compOpportunisticallyDependsOn(minimumIsa))
+    {
+        // The user disabled support for the baseline ISA so
+        // don't emit any SIMD intrinsics as they all require
+        // this at a minimum. We will, however, return false
+        // for IsHardwareAccelerated as that will help with
+        // dead code elimination.
+
+        return (intrinsicInfo->id == SIMDIntrinsicHWAccel) ? gtNewIconNode(0, TYP_INT) : nullptr;
+    }
+
     SIMDIntrinsicID simdIntrinsicID = intrinsicInfo->id;
     var_types       simdType;
     if (baseType != TYP_UNKNOWN)