gfx: drv: clean up the save/restore of the fp/mipi/dpll regs

We have an fp and dpll reg for pipe A and B. Pipe C shares pipe A's fp
and dpll setting, since the two pipes use the same clock setting. Store
these regs into the pipe_regs array instead of having separate names for
them. Pipe C's storage space will be wasted.

Pipe A and C has a MIPI control reg, store these into the pipe_regs
array. Pipe B's storage space will be wasted.

There is 12 bytes wasted, we pay this for a cleaner abstraction.

The original code saved the same dpll,fp regs twice (for pipe A and C)
now avoid saving/restoring them for pipe C. This may also avoid glitches
on the screen as we momentarily disabled pipe A's clock while it was
already setup and active.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h
index 876a93c..8c9259b 100644 (file)
--- a/drivers/staging/mrst/drv/psb_drv.h
+++ b/drivers/staging/mrst/drv/psb_drv.h
@@ -711,17 +711,16 @@ struct drm_psb_private {
                uint32_t dsp_status;
                uint32_t dsp_cntr;
                uint32_t pipe_conf;
+               uint32_t pll_ctrl;
+               uint32_t pll_div;
+               uint32_t mipi_ctrl;
                uint32_t palette[256];
        } pipe_regs[PSB_PIPE_NUM];
 
-       uint32_t saveFPA0;
        uint32_t saveFPA1;
-       uint32_t saveDPLL_A;
        uint32_t saveDPLL_A_MD;
        uint32_t saveDSPABASE;
-       uint32_t saveFPB0;
        uint32_t saveFPB1;
-       uint32_t saveDPLL_B;
        uint32_t saveDPLL_B_MD;
        uint32_t saveDSPBBASE;
        uint32_t saveVCLK_DIVISOR_VGA0;
@@ -826,8 +825,6 @@ struct drm_psb_private {
        uint32_t saveTXCLKESC_REG;
        uint32_t saveDPHY_PARAM_REG;
        uint32_t saveMIPI_CONTROL_REG;
-       uint32_t saveMIPI;
-       uint32_t saveMIPI_C;
        void (*init_drvIC)(struct drm_device *dev);
        void (*dsi_prePowerState)(struct drm_device *dev);
        void (*dsi_postPowerState)(struct drm_device *dev);

diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c
index 0b444ad..b966b8e 100644 (file)
--- a/drivers/staging/mrst/drv/psb_powermgmt.c
+++ b/drivers/staging/mrst/drv/psb_powermgmt.c
@@ -479,29 +479,17 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
        struct psb_pipe_regs *pr = &dev_priv->pipe_regs[pipe];
        int i;
 
-       /* regester */
-       u32 dpll_reg = MRST_DPLL_A;
-       u32 fp_reg = MRST_FPA0;
-       u32 mipi_reg = MIPI;
-
-       /* pointer to values */
-       u32 *dpll_val = &dev_priv->saveDPLL_A;
-       u32 *fp_val = &dev_priv->saveFPA0;
-       u32 *mipi_val = &dev_priv->saveMIPI;
        PSB_DEBUG_ENTRY("\n");
 
        switch (pipe) {
        case 0:
-               *mipi_val = PSB_RVDC32(mipi_reg);
+               pr->pll_ctrl = PSB_RVDC32(MRST_DPLL_A);
+               pr->pll_div = PSB_RVDC32(MRST_FPA0);
+               pr->mipi_ctrl = PSB_RVDC32(MIPI_PORT_CONTROL(pipe));
                break;
        case 1:
-               /* regester */
-               dpll_reg = MDFLD_DPLL_B;
-               fp_reg = MDFLD_DPLL_DIV0;
-
-               /* values */
-               dpll_val = &dev_priv->saveDPLL_B;
-               fp_val = &dev_priv->saveFPB0;
+               pr->pll_ctrl = PSB_RVDC32(MDFLD_DPLL_B);
+               pr->pll_div = PSB_RVDC32(MDFLD_DPLL_DIV0);
 
                dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
                dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
@@ -509,13 +497,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
                dev_priv->saveHDMIB_CONTROL = PSB_RVDC32(HDMIB_CONTROL);
                break;
        case 2:
-               /* regester */
-               mipi_reg = MIPI_C;
-
-               /* pointer to values */
-               mipi_val = &dev_priv->saveMIPI_C;
-
-               *mipi_val = PSB_RVDC32(mipi_reg);
+               pr->mipi_ctrl = PSB_RVDC32(MIPI_PORT_CONTROL(pipe));
                break;
        default:
                DRM_ERROR("%s, invalid pipe number. \n", __FUNCTION__);
@@ -523,8 +505,6 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
        }
 
        /* Pipe & plane A info */
-       *dpll_val = PSB_RVDC32(dpll_reg);
-       *fp_val = PSB_RVDC32(fp_reg);
        pr->pipe_conf = PSB_RVDC32(PSB_PIPECONF(pipe));
        pr->dsp_cntr = PSB_RVDC32(PSB_DSPCNTR(pipe));
 
@@ -596,40 +576,24 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
        struct mdfld_dsi_config * dsi_config = NULL;
        u32 i = 0;
        u32 dpll = 0;
+       u32 dpll_reg = 0;
+       u32 pll_div_reg = 0;
+       u32 dpll_val;
 
-       /* regester */
-       u32 dpll_reg = MRST_DPLL_A;
-       u32 fp_reg = MRST_FPA0;
-       u32 mipi_reg = MIPI;
-
-       /* values */
-       u32 dpll_val = dev_priv->saveDPLL_A & ~DPLL_VCO_ENABLE;
-       u32 fp_val = dev_priv->saveFPA0;
-       u32 mipi_val = dev_priv->saveMIPI;
        PSB_DEBUG_ENTRY("\n");
 
        switch (pipe) {
        case 0:
+               dpll_reg = MRST_DPLL_A;
+               pll_div_reg = MRST_FPA0;
                dsi_config = dev_priv->dsi_configs[0];
                break;
        case 1:
-               /* regester */
                dpll_reg = MDFLD_DPLL_B;
-               fp_reg = MDFLD_DPLL_DIV0;
-
-               /* values */
-               dpll_val = dev_priv->saveDPLL_B & ~DPLL_VCO_ENABLE;
-               fp_val = dev_priv->saveFPB0;
+               pll_div_reg = MDFLD_DPLL_DIV0;
                break;
        case 2:
                dsi_output = dev_priv->dbi_output2;
-
-               /* regester */
-               mipi_reg = MIPI_C;
-
-               /* values */
-               mipi_val = dev_priv->saveMIPI_C;
-
                dsi_config = dev_priv->dsi_configs[1];
                break;
        default:
@@ -637,16 +601,19 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
                return -EINVAL;
        }
 
+       dpll_val = pr->pll_ctrl & ~DPLL_VCO_ENABLE;
+
        /*make sure VGA plane is off. it initializes to on after reset!*/
        PSB_WVDC32(0x80000000, VGACNTRL);
 
-       if (pipe == 1) {
+       switch (pipe) {
+       case 1:
                PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg);
                PSB_RVDC32(dpll_reg);
+               PSB_WVDC32(pr->pll_div, pll_div_reg);
+               break;
 
-               PSB_WVDC32(fp_val, fp_reg);
-       } else {
-
+       case 0:
                dpll = PSB_RVDC32(dpll_reg);
 
                if (!(dpll & DPLL_VCO_ENABLE)) {
@@ -658,7 +625,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
                                udelay(500);
                        }
 
-                       PSB_WVDC32(fp_val, fp_reg);
+                       PSB_WVDC32(pr->pll_div, pll_div_reg);
                        PSB_WVDC32(dpll_val, dpll_reg);
                        /* FIXME_MDFLD PO - change 500 to 1 after PO */
                        udelay(500);
@@ -673,6 +640,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
                                return -EINVAL;
                        }
                }
+               break;
        }
 
        PSB_WVDC32(pr->htotal,          PSB_HTOTAL(pipe));
@@ -711,7 +679,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
        }
 
        /*set up pipe related registers*/
-       PSB_WVDC32(mipi_val, mipi_reg);
+       PSB_WVDC32(pr->mipi_ctrl, MIPI_PORT_CONTROL(pipe));
 
        /*setup MIPI adapter + MIPI IP registers*/
        if (dsi_config)
@@ -731,9 +699,9 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
                msleep(20);
 
        /* LP Hold Release */
-       temp = REG_READ(mipi_reg);
+       temp = REG_READ(MIPI_PORT_CONTROL(pipe));
        temp |= LP_OUTPUT_HOLD_RELEASE;
-       REG_WRITE(mipi_reg, temp);
+       REG_WRITE(MIPI_PORT_CONTROL(pipe), temp);
        mdelay(1);
 
        if (pipe == PSB_PIPE_A) {