drm/i915: don't save/restore DP regs for kms
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 17 Oct 2012 09:32:55 +0000 (11:32 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 17 Oct 2012 20:36:29 +0000 (22:36 +0200)
We completely compute these anew in each modeset, hence we don't rely
on them containing anything valid after resume.

To avoid breaking any ums setup due to reordering of the reads/writes
simply don't reorder anything, but bracket the reads/writes into if
(!kms) conditionals. More churn, but safer.

v2: Fixup the logic, noticed by Paulo Zanoni.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_suspend.c

index 4776ccf..69b2d7f 100644 (file)
@@ -654,21 +654,23 @@ static void i915_save_display(struct drm_device *dev)
                dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
        }
 
-       /* Display Port state */
-       if (SUPPORTS_INTEGRATED_DP(dev)) {
-               dev_priv->saveDP_B = I915_READ(DP_B);
-               dev_priv->saveDP_C = I915_READ(DP_C);
-               dev_priv->saveDP_D = I915_READ(DP_D);
-               dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
-               dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
-               dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
-               dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
-               dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
-               dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
-               dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
-               dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
-       }
-       /* FIXME: save TV & SDVO state */
+       if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+               /* Display Port state */
+               if (SUPPORTS_INTEGRATED_DP(dev)) {
+                       dev_priv->saveDP_B = I915_READ(DP_B);
+                       dev_priv->saveDP_C = I915_READ(DP_C);
+                       dev_priv->saveDP_D = I915_READ(DP_D);
+                       dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
+                       dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
+                       dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
+                       dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
+                       dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
+                       dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
+                       dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
+                       dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
+               }
+               /* FIXME: save TV & SDVO state */
+       }
 
        /* Only save FBC state on the platform that supports FBC */
        if (I915_HAS_FBC(dev)) {
@@ -703,16 +705,18 @@ static void i915_restore_display(struct drm_device *dev)
        /* Display arbitration */
        I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 
-       /* Display port ratios (must be done before clock is set) */
-       if (SUPPORTS_INTEGRATED_DP(dev)) {
-               I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
-               I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
-               I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
-               I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
-               I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
-               I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
-               I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
-               I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
+       if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+               /* Display port ratios (must be done before clock is set) */
+               if (SUPPORTS_INTEGRATED_DP(dev)) {
+                       I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
+                       I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
+                       I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
+                       I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
+                       I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
+                       I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
+                       I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
+                       I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
+               }
        }
 
        /* This is only meaningful in non-KMS mode */
@@ -761,13 +765,15 @@ static void i915_restore_display(struct drm_device *dev)
                I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
        }
 
-       /* Display Port state */
-       if (SUPPORTS_INTEGRATED_DP(dev)) {
-               I915_WRITE(DP_B, dev_priv->saveDP_B);
-               I915_WRITE(DP_C, dev_priv->saveDP_C);
-               I915_WRITE(DP_D, dev_priv->saveDP_D);
+       if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
+               /* Display Port state */
+               if (SUPPORTS_INTEGRATED_DP(dev)) {
+                       I915_WRITE(DP_B, dev_priv->saveDP_B);
+                       I915_WRITE(DP_C, dev_priv->saveDP_C);
+                       I915_WRITE(DP_D, dev_priv->saveDP_D);
+               }
+               /* FIXME: restore TV & SDVO state */
        }
-       /* FIXME: restore TV & SDVO state */
 
        /* only restore FBC info on the platform that supports FBC*/
        intel_disable_fbc(dev);