UNSPEC_MMA_XVI8GER4SPP
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
- UNSPEC_MMA_XXSETACCZ
+ ])
+
+(define_c_enum "unspecv"
+ [UNSPECV_MMA_XXSETACCZ
])
;; MMA instructions with 1 accumulator argument
"<acc> %A0"
[(set_attr "type" "mma")])
-;; We can't have integer constants in XOmode so we wrap this in an UNSPEC.
-
-(define_expand "mma_xxsetaccz"
- [(set (match_operand:XO 0 "fpr_reg_operand")
- (const_int 0))]
- "TARGET_MMA"
-{
- rtx xo0 = gen_rtx_UNSPEC (XOmode, gen_rtvec (1, const0_rtx),
- UNSPEC_MMA_XXSETACCZ);
- emit_insn (gen_rtx_SET (operands[0], xo0));
- DONE;
-})
+;; We can't have integer constants in XOmode so we wrap this in an
+;; UNSPEC_VOLATILE.
-(define_insn_and_split "*mma_xxsetaccz"
+(define_insn "mma_xxsetaccz"
[(set (match_operand:XO 0 "fpr_reg_operand" "=d")
- (unspec:XO [(match_operand 1 "const_0_to_1_operand" "O")]
- UNSPEC_MMA_XXSETACCZ))]
+ (unspec_volatile:XO [(const_int 0)]
+ UNSPECV_MMA_XXSETACCZ))]
"TARGET_MMA"
"xxsetaccz %A0"
- "&& reload_completed"
- [(set (match_dup 0) (unspec:XO [(match_dup 1)] UNSPEC_MMA_XXSETACCZ))]
- ""
- [(set_attr "type" "mma")
- (set_attr "length" "4")])
+ [(set_attr "type" "mma")])
(define_insn "mma_<vv>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
void
foo (__vector_quad *dst)
{
- __vector_quad acc;
- __builtin_mma_xxsetaccz (&acc);
- *dst = acc;
+ __vector_quad acc0, acc1;
+ __builtin_mma_xxsetaccz (&acc0);
+ __builtin_mma_xxsetaccz (&acc1);
+ dst[0] = acc0;
+ dst[1] = acc1;
}
/* { dg-final { scan-assembler-not {\mlxv\M} } } */
/* { dg-final { scan-assembler-not {\mlxvp\M} } } */
/* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */
-/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxmfacc\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */