w1: mxc_w1: Optimize mxc_w1_ds2_touch_bit()

According to the i.MX reference manual, the read/write bit operations
takes from 60 us to 120 us.
This patch optimizes mxc_w1_ds2_touch_bit() function to use proper
value for such delay. Nevertheless, a small margin for the timeout has
been added for the case if clock frequency is inaccurate.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 741d2bb..da3d0f0 100644 (file)
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -75,22 +75,25 @@ static u8 mxc_w1_ds2_reset_bus(void *data)
  */
 static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
 {
-       struct mxc_w1_device *mdev = data;
-       void __iomem *ctrl_addr = mdev->regs + MXC_W1_CONTROL;
-       unsigned int timeout_cnt = 400; /* Takes max. 120us according to
-                                        * datasheet.
-                                        */
+       struct mxc_w1_device *dev = data;
+       unsigned long timeout;
+
+       writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
+
+       /* Wait for read/write bit (60us, Max 120us), use 200us for sure */
+       timeout = jiffies + usecs_to_jiffies(200);
 
-       writeb(MXC_W1_CONTROL_WR(bit), ctrl_addr);
+       udelay(60);
 
-       while (timeout_cnt--) {
-               if (!(readb(ctrl_addr) & MXC_W1_CONTROL_WR(bit)))
-                       break;
+       do {
+               u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
 
-               udelay(1);
-       }
+               /* RDST bit is valid after the WR1/RD bit is self-cleared */
+               if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
+                       return !!(ctrl & MXC_W1_CONTROL_RDST);
+       } while (time_is_after_jiffies(timeout));
 
-       return !!(readb(ctrl_addr) & MXC_W1_CONTROL_RDST);
+       return 0;
 }
 
 static int mxc_w1_probe(struct platform_device *pdev)