KVM: x86/mmu: Apply max PA check for MMIO sptes to 32-bit KVM
authorSean Christopherson <sean.j.christopherson@intel.com>
Wed, 8 Jan 2020 00:12:10 +0000 (16:12 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 11 Feb 2020 12:35:53 +0000 (04:35 -0800)
[ Upstream commit e30a7d623dccdb3f880fbcad980b0cb589a1da45 ]

Remove the bogus 64-bit only condition from the check that disables MMIO
spte optimization when the system supports the max PA, i.e. doesn't have
any reserved PA bits.  32-bit KVM always uses PAE paging for the shadow
MMU, and per Intel's SDM:

  PAE paging translates 32-bit linear addresses to 52-bit physical
  addresses.

The kernel's restrictions on max physical addresses are limits on how
much memory the kernel can reasonably use, not what physical addresses
are supported by hardware.

Fixes: ce88decffd17 ("KVM: MMU: mmio page fault support")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/x86/kvm/mmu.c

index 2ce9da5..3644ac2 100644 (file)
@@ -6249,7 +6249,7 @@ static void kvm_set_mmio_spte_mask(void)
         * If reserved bit is not supported, clear the present bit to disable
         * mmio page fault.
         */
-       if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52)
+       if (shadow_phys_bits == 52)
                mask &= ~1ull;
 
        kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);