freedreno/regs: add bit to control continuous clock with 7nm PHYs

7nm PHYs need another special bit set in DSI_LANE_CTRL to enable
continuous DSI clock. Document this bit.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11219>

diff --git a/src/freedreno/registers/dsi/dsi.xml b/src/freedreno/registers/dsi/dsi.xml
index 90f1a29..a2a51c6 100644 (file)
--- a/src/freedreno/registers/dsi/dsi.xml
+++ b/src/freedreno/registers/dsi/dsi.xml
@@ -271,6 +271,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
                <bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
        </reg32>
        <reg32 offset="0x000a8" name="LANE_CTRL">
+               <bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
                <bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
        </reg32>
        <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">