arm64: dts: qcom: sm8150: Add Crypto Engine support

Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8150.dtsi'.

Tested-by: Anders Roxell <anders.roxell@linaro.org>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526192210.3146896-9-bhupesh.sharma@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 2c377d7..2a5b2b9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2085,6 +2085,36 @@
                        };
                };
 
+               cryptobam: dma-controller@1dc4000 {
+                       compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+                       reg = <0 0x01dc4000 0 0x24000>;
+                       interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       qcom,ee = <0>;
+                       qcom,controlled-remotely;
+                       num-channels = <8>;
+                       qcom,num-ees = <2>;
+                       iommus = <&apps_smmu 0x502 0x0641>,
+                                <&apps_smmu 0x504 0x0011>,
+                                <&apps_smmu 0x506 0x0011>,
+                                <&apps_smmu 0x508 0x0011>,
+                                <&apps_smmu 0x512 0x0000>;
+               };
+
+               crypto: crypto@1dfa000 {
+                       compatible = "qcom,sm8150-qce", "qcom,qce";
+                       reg = <0 0x01dfa000 0 0x6000>;
+                       dmas = <&cryptobam 4>, <&cryptobam 5>;
+                       dma-names = "rx", "tx";
+                       iommus = <&apps_smmu 0x502 0x0641>,
+                                <&apps_smmu 0x504 0x0011>,
+                                <&apps_smmu 0x506 0x0011>,
+                                <&apps_smmu 0x508 0x0011>,
+                                <&apps_smmu 0x512 0x0000>;
+                       interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+                       interconnect-names = "memory";
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x20000>;