arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194

Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 5f81328..fe58866 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1538,6 +1538,21 @@
                        iommus = <&smmu TEGRA186_SID_VIC>;
                };
 
+               nvjpg@15380000 {
+                       compatible = "nvidia,tegra186-nvjpg";
+                       reg = <0x15380000 0x40000>;
+                       clocks = <&bpmp TEGRA186_CLK_NVJPG>;
+                       clock-names = "nvjpg";
+                       resets = <&bpmp TEGRA186_RESET_NVJPG>;
+                       reset-names = "nvjpg";
+
+                       power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
+                       interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
+                                       <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
+                       interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA186_SID_NVJPG>;
+               };
+
                dsib: dsi@15400000 {
                        compatible = "nvidia,tegra186-dsi";
                        reg = <0x15400000 0x10000>;
@@ -1569,6 +1584,21 @@
                        iommus = <&smmu TEGRA186_SID_NVDEC>;
                };
 
+               nvenc@154c0000 {
+                       compatible = "nvidia,tegra186-nvenc";
+                       reg = <0x154c0000 0x40000>;
+                       clocks = <&bpmp TEGRA186_CLK_NVENC>;
+                       clock-names = "nvenc";
+                       resets = <&bpmp TEGRA186_RESET_NVENC>;
+                       reset-names = "nvenc";
+
+                       power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
+                       interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
+                                       <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
+                       interconnect-names = "dma-mem", "write";
+                       iommus = <&smmu TEGRA186_SID_NVENC>;
+               };
+
                sor0: sor@15540000 {
                        compatible = "nvidia,tegra186-sor";
                        reg = <0x15540000 0x10000>;

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 3b42449..c97febf 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1739,6 +1739,22 @@
                                iommus = <&smmu TEGRA194_SID_VIC>;
                        };
 
+                       nvjpg@15380000 {
+                               compatible = "nvidia,tegra194-nvjpg";
+                               reg = <0x15380000 0x40000>;
+                               clocks = <&bpmp TEGRA194_CLK_NVJPG>;
+                               clock-names = "nvjpg";
+                               resets = <&bpmp TEGRA194_RESET_NVJPG>;
+                               reset-names = "nvjpg";
+
+                               power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
+                               interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
+                               interconnect-names = "dma-mem", "write";
+                               iommus = <&smmu TEGRA194_SID_NVJPG>;
+                               dma-coherent;
+                       };
+
                        nvdec@15480000 {
                                compatible = "nvidia,tegra194-nvdec";
                                reg = <0x15480000 0x00040000>;
@@ -1758,6 +1774,25 @@
                                nvidia,host1x-class = <0xf0>;
                        };
 
+                       nvenc@154c0000 {
+                               compatible = "nvidia,tegra194-nvenc";
+                               reg = <0x154c0000 0x40000>;
+                               clocks = <&bpmp TEGRA194_CLK_NVENC>;
+                               clock-names = "nvenc";
+                               resets = <&bpmp TEGRA194_RESET_NVENC>;
+                               reset-names = "nvenc";
+
+                               power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
+                               interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
+                               interconnect-names = "dma-mem", "read-1", "write";
+                               iommus = <&smmu TEGRA194_SID_NVENC>;
+                               dma-coherent;
+
+                               nvidia,host1x-class = <0x21>;
+                       };
+
                        dpaux0: dpaux@155c0000 {
                                compatible = "nvidia,tegra194-dpaux";
                                reg = <0x155c0000 0x10000>;
@@ -1894,6 +1929,25 @@
                                };
                        };
 
+                       nvenc@15a80000 {
+                               compatible = "nvidia,tegra194-nvenc";
+                               reg = <0x15a80000 0x00040000>;
+                               clocks = <&bpmp TEGRA194_CLK_NVENC1>;
+                               clock-names = "nvenc";
+                               resets = <&bpmp TEGRA194_RESET_NVENC1>;
+                               reset-names = "nvenc";
+
+                               power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
+                               interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
+                               interconnect-names = "dma-mem", "read-1", "write";
+                               iommus = <&smmu TEGRA194_SID_NVENC1>;
+                               dma-coherent;
+
+                               nvidia,host1x-class = <0x22>;
+                       };
+
                        sor0: sor@15b00000 {
                                compatible = "nvidia,tegra194-sor";
                                reg = <0x15b00000 0x40000>;