ARM: dts: ZII: Disable HW Ethernet switch reset GPIOs
authorChris Healy <cphealy@gmail.com>
Wed, 22 Jul 2020 20:33:41 +0000 (13:33 -0700)
committerShawn Guo <shawnguo@kernel.org>
Mon, 17 Aug 2020 13:28:42 +0000 (21:28 +0800)
Disable Ethernet switch reset GPIO with ZII platforms that have it
enabled.  HW switch reset results in a reset of the copper PHYs
inside of the switch.  We want to avoid this reset of the copper PHYs
in the switch as this results in unnecessary broader network disruption on
a soft reboot of the application processor.

With the HW GPIO removed, the switch driver still performs a soft reset of
the switch core which has been shown to sufficiently meet our needs with
other ZII platforms that do not have the HW switch reset GPIO defined.

Signed-off-by: Chris Healy <cphealy@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/vf610-zii-cfu1.dts
arch/arm/boot/dts/vf610-zii-spb4.dts
arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

index 64e0e95..50da0c9 100644 (file)
                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
-                       reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 
                        ports {
                                #address-cells = <1>;
        pinctrl_switch: switch-grp {
                fsl,pins = <
                        VF610_PAD_PTB28__GPIO_98                0x3061
-                       VF610_PAD_PTE2__GPIO_107                0x1042
                >;
        };
 
index 9e5187b..6c6ec46 100644 (file)
                        pinctrl-names = "default";
                        reg = <0>;
                        eeprom-length = <65536>;
-                       reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
                        interrupt-parent = <&gpio3>;
                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                        interrupt-controller;
 
        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
                fsl,pins = <
-                       VF610_PAD_PTE2__GPIO_107                0x31c2
                        VF610_PAD_PTB28__GPIO_98                0x219d
                >;
        };
index 569614b..73fdace 100644 (file)
                        pinctrl-names = "default";
                        reg = <0>;
                        eeprom-length = <65536>;
-                       reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
                        interrupt-parent = <&gpio3>;
                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                        interrupt-controller;
 
        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
                fsl,pins = <
-                       VF610_PAD_PTE2__GPIO_107                0x31c2
                        VF610_PAD_PTB28__GPIO_98                0x219d
                >;
        };
index b6b0f30..fe600ab 100644 (file)
                        pinctrl-names = "default";
                        reg = <0>;
                        eeprom-length = <65536>;
-                       reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
                        interrupt-parent = <&gpio3>;
                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                        interrupt-controller;
 
        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
                fsl,pins = <
-                       VF610_PAD_PTE2__GPIO_107                0x31c2
                        VF610_PAD_PTB28__GPIO_98                0x219d
                >;
        };