phy/rockchip: inno-hdmi: force set_rate on power_on

Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
not in pixel clock rate.
When the hdmiphy clock is configured with the same pixel clock rate using
clk_set_rate() the clock framework do not signal the hdmi phy driver
to set_rate when switching between 8-bit and Deep Color.
This result in pre/post pll not being re-configured when switching between
regular 8-bit and Deep Color video formats.

Fix this by calling set_rate in power_on to force pre pll re-configuration.

Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index fe7fa9a43ec0a5ebd042373dbc8110ca87b1db48..a1fb39af649348bb020217c0175be9f9896071c9 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
        struct clk_hw hw;
        struct clk *phyclk;
        unsigned long pixclock;
+       unsigned long tmdsclock;
 };
 
 struct pre_pll_config {
@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
 
        dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
 
+       inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
+
        ret = clk_prepare_enable(inno->phyclk);
        if (ret)
                return ret;
@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy)
 
        clk_disable_unprepare(inno->phyclk);
 
+       inno->tmdsclock = 0;
+
        dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
 
        return 0;
@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
        dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
                __func__, rate, tmdsclock);
 
+       if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
+               return 0;
+
        cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
        if (IS_ERR(cfg))
                return PTR_ERR(cfg);
@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
        }
 
        inno->pixclock = rate;
+       inno->tmdsclock = tmdsclock;
 
        return 0;
 }
@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
        dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
                __func__, rate, tmdsclock);
 
+       if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
+               return 0;
+
        cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
        if (IS_ERR(cfg))
                return PTR_ERR(cfg);
@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
        }
 
        inno->pixclock = rate;
+       inno->tmdsclock = tmdsclock;
 
        return 0;
 }