if (lcd_drv->lcd_status & LCD_STATUS_ENCL_ON) {
aml_lcd_notifier_call_chain(
LCD_EVENT_IF_POWER_ON, NULL);
+ lcd_if_enable_retry(lcd_drv->lcd_config);
} else {
LCDERR("%s: can't power on when controller is off\n",
__func__);
if (temp) {
mutex_lock(&lcd_drv->power_mutex);
aml_lcd_notifier_call_chain(LCD_EVENT_POWER_ON, NULL);
+ lcd_if_enable_retry(lcd_drv->lcd_config);
mutex_unlock(&lcd_drv->power_mutex);
} else {
mutex_lock(&lcd_drv->power_mutex);
struct class_attribute *attr, char *buf)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ unsigned int state_save;
- return sprintf(buf, "state: %d, check_en: %d\n",
+ state_save = lcd_vcbus_getb(L_VCOM_VS_ADDR, 12, 1);
+
+ return sprintf(buf, "state: %d, check_en: %d, state_save: %d\n",
lcd_drv->lcd_config->lcd_control.mipi_config->check_state,
- lcd_drv->lcd_config->lcd_control.mipi_config->check_en);
+ lcd_drv->lcd_config->lcd_control.mipi_config->check_en,
+ state_save);
}
static struct class_attribute lcd_interface_debug_class_attrs[] = {
#define MIPI_DSI_COLOR_18BIT COLOR_18BIT_CFG_2
#define MIPI_DSI_COLOR_24BIT COLOR_24BIT
#define MIPI_DSI_TEAR_SWITCH MIPI_DCS_DISABLE_TEAR
-#define CMD_TIMEOUT_CNT 3000
+#define CMD_TIMEOUT_CNT 5000
/* ************************************************************* */
static char *operation_mode_table[] = {
/* Trigger a sync active for esc_clk */
dsi_phy_set_mask(MIPI_DSI_PHY_CTRL, (1 << 1));
- /* Startup transfer */
+ /* Startup transfer, default lpclk */
dsi_host_write(MIPI_DSI_DWC_LPCLK_CTRL_OS,
(0x1 << BIT_AUTOCLKLANE_CTRL) |
(0x1 << BIT_TXREQUESTCLKHS));
(1 << BIT_LP_VBP_EN) | /* enalbe lp */
(1 << BIT_LP_VSA_EN) | /* enalbe lp */
(0 << BIT_FRAME_BTA_ACK_EN) |
- /* enable BTA after one frame, TODO, need check */
+ /* enable BTA after one frame, TODO, need check */
/* (1 << BIT_LP_CMD_EN) | */
/* enable the command transmission only in lp mode */
(vid_mode_type << BIT_VID_MODE_TYPE));
* Function: wait_cmd_fifo_empty
* Poll to check if the generic command fifo is empty
*/
-static void wait_cmd_fifo_empty(void)
+static int wait_cmd_fifo_empty(void)
{
unsigned int cmd_status;
int i = CMD_TIMEOUT_CNT;
do {
udelay(10);
i--;
+ cmd_status = dsi_host_getb(MIPI_DSI_DWC_CMD_PKT_STATUS_OS,
+ BIT_GEN_CMD_EMPTY, 1);
+ } while ((cmd_status != 0x1) && (i > 0));
+
+ if (cmd_status == 0) {
cmd_status = dsi_host_read(MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
- } while ((((cmd_status >> BIT_GEN_CMD_EMPTY) & 0x1) != 0x1) && (i > 0));
- print_mipi_cmd_status(i, cmd_status);
+ print_mipi_cmd_status(i, cmd_status);
+ return -1;
+ }
+
+ return 0;
}
#if 0
DT_GEN_SHORT_WR_1,
DT_GEN_SHORT_WR_2,
*/
-static void dsi_generic_write_short_packet(struct dsi_cmd_request_s *req)
+static int dsi_generic_write_short_packet(struct dsi_cmd_request_s *req)
{
unsigned int d_para[2];
+ int ret = 0;
switch (req->data_type) {
case DT_GEN_SHORT_WR_1:
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- wait_bta_ack();
+ ret = wait_bta_ack();
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty();
+
+ return ret;
}
/* *************************************************************
* DCS Write Short Packet with Generic Interface
* Supported Data Type: DT_DCS_SHORT_WR_0, DT_DCS_SHORT_WR_1,
*/
-static void dsi_dcs_write_short_packet(struct dsi_cmd_request_s *req)
+static int dsi_dcs_write_short_packet(struct dsi_cmd_request_s *req)
{
unsigned int d_command, d_para;
+ int ret = 0;
d_command = ((unsigned int)req->payload[2]) & 0xff;
d_para = (req->pld_count < 2) ?
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- wait_bta_ack();
+ ret = wait_bta_ack();
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty();
+
+ return ret;
}
/* *************************************************************
* Write Long Packet with Generic Interface
* Supported Data Type: DT_GEN_LONG_WR, DT_DCS_LONG_WR
*/
-static void dsi_write_long_packet(struct dsi_cmd_request_s *req)
+static int dsi_write_long_packet(struct dsi_cmd_request_s *req)
{
unsigned int d_command, payload_data, header_data;
unsigned int cmd_status;
unsigned int i, j, data_index, n, temp;
+ int ret = 0;
/* payload[2] start (payload[0]: data_type, payload[1]: data_cnt) */
data_index = DSI_CMD_SIZE_INDEX + 1;
(((unsigned int)req->data_type) << BIT_GEN_DT));
generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS, header_data);
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- wait_bta_ack();
+ ret = wait_bta_ack();
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty();
+
+ return ret;
}
#ifdef DSI_CMD_READ_VALID
}
#endif
-static void mipi_dsi_check_state(unsigned char reg, int cnt)
+static int mipi_dsi_check_state(unsigned char reg, int cnt)
{
int ret = 0, i, len;
unsigned char *rd_data;
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
if (lcd_drv->lcd_config->lcd_control.mipi_config->check_en == 0)
- return;
+ return 0;
LCDPR("%s\n", __func__);
rd_data = kmalloc_array(cnt, sizeof(unsigned char), GFP_KERNEL);
if (rd_data == NULL) {
LCDERR("%s: rd_data error\n", __func__);
- return;
+ return 0;
}
payload[2] = reg;
lcd_drv->lcd_config->lcd_control.mipi_config->check_state = 0;
lcd_vcbus_setb(L_VCOM_VS_ADDR, 0, 12, 1);
kfree(rd_data);
- return;
+ return -1;
}
if (ret > cnt) {
LCDERR("%s: read back cnt is wrong\n", __func__);
kfree(rd_data);
- return;
+ return -1;
}
lcd_drv->lcd_config->lcd_control.mipi_config->check_state = 1;
pr_info("%s\n", str);
kfree(rd_data);
+ return 0;
}
/* *************************************************************
struct dsi_cmd_request_s dsi_cmd_req;
unsigned char vc_id = MIPI_DSI_VIRTUAL_CHAN_ID;
unsigned int req_ack = MIPI_DSI_DCS_ACK_TYPE;
+ int ret = 0;
/* mipi command(payload) */
/* format: data_type, cmd_size, data.... */
* data0=gpio_index, data1=gpio_value, data2=delay.
*/
while (i < DSI_CMD_SIZE_MAX) {
+ if (ret) {
+ LCDERR("%s: error, exit\n", __func__);
+ break;
+ }
if (payload[i] == 0xff) {
j = 2;
if (payload[i+1] == 0xff)
break;
}
if (payload[i+DSI_GPIO_INDEX+2] > 0) {
- mipi_dsi_check_state(
+ ret = mipi_dsi_check_state(
payload[i+DSI_GPIO_INDEX],
payload[i+DSI_GPIO_INDEX+1]);
}
case DT_GEN_SHORT_WR_0:
case DT_GEN_SHORT_WR_1:
case DT_GEN_SHORT_WR_2:
- dsi_generic_write_short_packet(&dsi_cmd_req);
+ ret = dsi_generic_write_short_packet(
+ &dsi_cmd_req);
break;
case DT_DCS_SHORT_WR_0:
case DT_DCS_SHORT_WR_1:
- dsi_dcs_write_short_packet(&dsi_cmd_req);
+ ret = dsi_dcs_write_short_packet(&dsi_cmd_req);
break;
case DT_DCS_LONG_WR:
case DT_GEN_LONG_WR:
- dsi_write_long_packet(&dsi_cmd_req);
+ ret = dsi_write_long_packet(&dsi_cmd_req);
break;
case DT_TURN_ON:
dsi_host_setb(MIPI_DSI_TOP_CNTL, 1, 2, 1);
}
#endif
+ if (dconf->check_en) {
+ if (dconf->check_state == 0)
+ pconf->retry_enable = 1;
+ else
+ pconf->retry_enable = 0;
+ }
+
if (op_mode_disp != op_mode_init) {
set_mipi_dsi_host(MIPI_DSI_VIRTUAL_CHAN_ID,
0, /* Chroma sub sample, only for