Undo incorrect fix of typos regarding 'an' article

(revert part of commit cbde60d)

* src/atomic_ops/sysdeps/icc/ia64.h (AO_char_load_acquire): Fix typo
("an ld.acq") in comment.
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
(AO_XSIZE_load_acquire): Likewise.
* src/atomic_ops/sysdeps/icc/ia64.h (AO_short_load_acquire,
AO_int_load_acquire): Add comment (similar to that of
AO_char_load_acquire).
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
(AO_XSIZE_store_release): Fix typo ("an st.rel") in comment.
* src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h:
Regenerate.
* src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h:
Likewise.
* src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h:
Likewise.
* src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h:
Likewise.

diff --git a/src/atomic_ops/sysdeps/icc/ia64.h b/src/atomic_ops/sysdeps/icc/ia64.h
index 328f9b4..6654209 100644 (file)
--- a/src/atomic_ops/sysdeps/icc/ia64.h
+++ b/src/atomic_ops/sysdeps/icc/ia64.h
@@ -55,7 +55,7 @@ AO_store_release(volatile AO_t *p, AO_t val)
 AO_INLINE unsigned char
 AO_char_load_acquire(const volatile unsigned char *p)
 {
-  /* A normal volatile load generates a ld.acq instruction.     */
+  /* A normal volatile load generates an ld.acq         */
   return (__ld1_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_char_load_acquire
@@ -70,6 +70,7 @@ AO_char_store_release(volatile unsigned char *p, unsigned char val)
 AO_INLINE unsigned short
 AO_short_load_acquire(const volatile unsigned short *p)
 {
+  /* A normal volatile load generates an ld.acq         */
   return (__ld2_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_short_load_acquire
@@ -84,6 +85,7 @@ AO_short_store_release(volatile unsigned short *p, unsigned short val)
 AO_INLINE unsigned int
 AO_int_load_acquire(const volatile unsigned int *p)
 {
+  /* A normal volatile load generates an ld.acq         */
   return (__ld4_acq((AO_INTEL_PTR_t)p));
 }
 #define AO_HAVE_int_load_acquire

diff --git a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
index 3c7341e..51c8560 100644 (file)
--- a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_load_acquire(const volatile AO_t *addr)
 {
   AO_t result = *addr;
 
-  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
+  /* A normal volatile load generates an ld.acq (on IA-64).     */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_store_release(volatile AO_t *addr, AO_t new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates a st.rel instruction (on IA-64). */
+  /* A normal volatile store generates an st.rel (on IA-64).    */
   *addr = new_val;
 }
 #define AO_HAVE_store_release

diff --git a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
index a7dfd15..10f45a9 100644 (file)
--- a/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
+++ b/src/atomic_ops/sysdeps/loadstore/acquire_release_volatile.template
@@ -45,7 +45,7 @@ AO_XSIZE_load_acquire(const volatile XCTYPE *addr)
 {
   XCTYPE result = *addr;
 
-  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
+  /* A normal volatile load generates an ld.acq (on IA-64).     */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_XSIZE_store_release(volatile XCTYPE *addr, XCTYPE new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates a st.rel instruction (on IA-64). */
+  /* A normal volatile store generates an st.rel (on IA-64).    */
   *addr = new_val;
 }
 #define AO_HAVE_XSIZE_store_release

diff --git a/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
index 1a23058..6de6b8a 100644 (file)
--- a/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/char_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_char_load_acquire(const volatile unsigned/**/char *addr)
 {
   unsigned/**/char result = *addr;
 
-  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
+  /* A normal volatile load generates an ld.acq (on IA-64).     */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_char_store_release(volatile unsigned/**/char *addr, unsigned/**/char new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates a st.rel instruction (on IA-64). */
+  /* A normal volatile store generates an st.rel (on IA-64).    */
   *addr = new_val;
 }
 #define AO_HAVE_char_store_release

diff --git a/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
index 18a7e4b..6b4875d 100644 (file)
--- a/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/int_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_int_load_acquire(const volatile unsigned *addr)
 {
   unsigned result = *addr;
 
-  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
+  /* A normal volatile load generates an ld.acq (on IA-64).     */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_int_store_release(volatile unsigned *addr, unsigned new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates a st.rel instruction (on IA-64). */
+  /* A normal volatile store generates an st.rel (on IA-64).    */
   *addr = new_val;
 }
 #define AO_HAVE_int_store_release

diff --git a/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h b/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
index 19f7781..e753133 100644 (file)
--- a/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
+++ b/src/atomic_ops/sysdeps/loadstore/short_acquire_release_volatile.h
@@ -45,7 +45,7 @@ AO_short_load_acquire(const volatile unsigned/**/short *addr)
 {
   unsigned/**/short result = *addr;
 
-  /* A normal volatile load generates a ld.acq instruction (on IA-64).  */
+  /* A normal volatile load generates an ld.acq (on IA-64).     */
   AO_GCC_BARRIER();
   return result;
 }
@@ -55,7 +55,7 @@ AO_INLINE void
 AO_short_store_release(volatile unsigned/**/short *addr, unsigned/**/short new_val)
 {
   AO_GCC_BARRIER();
-  /* A normal volatile store generates a st.rel instruction (on IA-64). */
+  /* A normal volatile store generates an st.rel (on IA-64).    */
   *addr = new_val;
 }
 #define AO_HAVE_short_store_release