cris: Add break support for v10.

Still no retb

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>

diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index a760367..73004af 100644 (file)
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -64,6 +64,7 @@
 #define PR_NRP 12
 #define PR_CCS 13
 #define PR_USP 14
+#define PRV10_BRP 14
 #define PR_SPC 15
 
 /* CPU flags.  */

diff --git a/target-cris/helper.c b/target-cris/helper.c
index 8680f43..dcc19ef 100644 (file)
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -121,14 +121,14 @@ static void do_interruptv10(CPUCRISState *env)
                        /* These exceptions are genereated by the core itself.
                           ERP should point to the insn following the brk.  */
                        ex_vec = env->trap_vector;
-                       env->pregs[PR_ERP] = env->pc;
+                       env->pregs[PRV10_BRP] = env->pc;
                        break;
 
                case EXCP_NMI:
                        /* NMI is hardwired to vector zero.  */
                        ex_vec = 0;
                        env->pregs[PR_CCS] &= ~M_FLAG;
-                       env->pregs[PR_NRP] = env->pc;
+                       env->pregs[PRV10_BRP] = env->pc;
                        break;
 
                case EXCP_BUSFAULT:

diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 4ada3ed..3629629 100644 (file)
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1132,6 +1132,7 @@ static unsigned int dec10_ind(DisasContext *dc)
                     LOG_DIS("break %d\n", dc->src);
                     cris_evaluate_flags(dc);
                     tcg_gen_movi_tl(env_pc, dc->pc + 2);
+                    t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2));
                     t_gen_raise_exception(EXCP_BREAK);
                     dc->is_jmp = DISAS_UPDATE;
                     return insn_len;