return 0;
}
-void dcn315_clk_mgr_helper_populate_bw_params(
+static void dcn315_clk_mgr_helper_populate_bw_params(
struct clk_mgr_internal *clk_mgr,
struct integrated_info *bios_info,
const DpmClocks_315_t *clock_table)
return res_val;
}
-int dcn315_smu_send_msg_with_param(
+static int dcn315_smu_send_msg_with_param(
struct clk_mgr_internal *clk_mgr,
unsigned int msg_id, unsigned int param)
{
return actual_dispclk_set_mhz * 1000;
}
-int dcn315_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
-{
- int actual_phypclk_set_mhz = -1;
-
- if (!clk_mgr->smu_present && requested_phyclk_khz)
- return requested_phyclk_khz;
-
- /* Unit of SMU msg parameter is Mhz */
- actual_phypclk_set_mhz = dcn315_smu_send_msg_with_param(
- clk_mgr,
- VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
- khz_to_mhz_ceil(requested_phyclk_khz));
-
- return actual_phypclk_set_mhz * 1000;
-}
int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
{
#define DCN_BASE__INST0_SEG4 0x02403C00
#define DCN_BASE__INST0_SEG5 0
-enum dc_irq_source to_dal_irq_source_dcn315(
+static enum dc_irq_source to_dal_irq_source_dcn315(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id)