hdmirx: change irq toggle mode [1/1]
authorLei Yang <lei.yang@amlogic.com>
Wed, 13 Mar 2019 07:26:05 +0000 (15:26 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Thu, 14 Mar 2019 11:05:21 +0000 (03:05 -0800)
PD#SWPL-5224

Problem:
missing DRM irq.

Solution:
1. modify irq toggle mode.
2. add double check for IP irq bit.

Verify:
T962x2

Change-Id: I6c77e5da92d5f21bc3710d9a6a744c10b1895e71
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
arch/arm/boot/dts/amlogic/tl1_pxp.dts
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301.dts
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c

index cc776f8..10c2bfe 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index e3d901f..55b05ea 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index 73621c6..1e21585 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index 402275a..a64b99c 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index fe252bb..f7db8d3 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index cf68cd9..1df3a45 100644 (file)
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 41 1>;
+               interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
index 6b9c84c..55f57c0 100644 (file)
@@ -34,7 +34,7 @@
 #include "hdmi_rx_edid.h"
 
 
-#define RX_VER0 "ver.2019-01-22"
+#define RX_VER0 "ver.2019-03-13"
 /*
  *
  *
index f7fba04..0d3b6ad 100644 (file)
@@ -576,6 +576,14 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
        if (rx.chip_id != CHIP_ID_TL1) {
                if (error == 1)
                        goto reisr;
+       } else {
+               hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
+               hdmirx_top_intr_stat &= 0x1;
+               if (hdmirx_top_intr_stat) {
+                       if (log_level & ERR_LOG)
+                               rx_pr("\n irq_miss");
+                       goto reisr;
+               }
        }
        /* check the ip interrupt again */
        /*hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);