pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
- interrupts = <0 41 1>;
+ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,
<&clkc CLKID_HDMIRX_ACR_COMP>,
#include "hdmi_rx_edid.h"
-#define RX_VER0 "ver.2019-01-22"
+#define RX_VER0 "ver.2019-03-13"
/*
*
*
if (rx.chip_id != CHIP_ID_TL1) {
if (error == 1)
goto reisr;
+ } else {
+ hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
+ hdmirx_top_intr_stat &= 0x1;
+ if (hdmirx_top_intr_stat) {
+ if (log_level & ERR_LOG)
+ rx_pr("\n irq_miss");
+ goto reisr;
+ }
}
/* check the ip interrupt again */
/*hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);