drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 90e6c28..1c0b1aa 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -33,7 +33,7 @@
 
 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 {
-       return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
+       return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
 }
 
 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
@@ -188,7 +188,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
@@ -209,12 +209,12 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
                                PAGE_TABLE_BLOCK_SIZE,
                                adev->vm_manager.block_size - 9);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
                        lower_32_bits(adev->vm_manager.max_pfn - 1));
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
                        upper_32_bits(adev->vm_manager.max_pfn - 1));
        }
 }
@@ -224,12 +224,10 @@ static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
        unsigned i;
 
        for (i = 0 ; i < 18; ++i) {
-               WREG32(SOC15_REG_OFFSET(GC, 0,
-                                       mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
-                      2 * i, 0xffffffff);
-               WREG32(SOC15_REG_OFFSET(GC, 0,
-                                       mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
-                      2 * i, 0x1f);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+                                   2 * i, 0xffffffff);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+                                   2 * i, 0x1f);
        }
 }
 
@@ -268,7 +266,7 @@ void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 
        /* Disable all tables */
        for (i = 0; i < 16; i++)
-               WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
 
        /* Setup TLB control */
        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);