clk: qcom: gpucc-sm6350: Introduce index-based clk lookup

Add the nowadays-prefered and marginally faster way of looking up parent
clocks in the device tree. It also allows for clock-names-independent
operation, so long as the order (which is enforced by schema) is kept.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-1-afcdfb18bb13@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c
index ef15185a99c313e497f7166b5f56d249707e000e..a9887d1f0ed71fb6ddc707f683616dfbaa9b16d5 100644 (file)
--- a/drivers/clk/qcom/gpucc-sm6350.c
+++ b/drivers/clk/qcom/gpucc-sm6350.c
@@ -24,6 +24,12 @@
 #define CX_GMU_CBCR_WAKE_MASK          0xF
 #define CX_GMU_CBCR_WAKE_SHIFT         8
 
+enum {
+       DT_BI_TCXO,
+       DT_GPLL0_OUT_MAIN,
+       DT_GPLL0_OUT_MAIN_DIV,
+};
+
 enum {
        P_BI_TCXO,
        P_GPLL0_OUT_MAIN,
@@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
                .hw.init = &(struct clk_init_data){
                        .name = "gpu_cc_pll0",
                        .parent_data =  &(const struct clk_parent_data){
+                               .index = DT_BI_TCXO,
                                .fw_name = "bi_tcxo",
                        },
                        .num_parents = 1,
@@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
                .hw.init = &(struct clk_init_data){
                        .name = "gpu_cc_pll1",
                        .parent_data =  &(const struct clk_parent_data){
+                               .index = DT_BI_TCXO,
                                .fw_name = "bi_tcxo",
                        },
                        .num_parents = 1,
@@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = {
 };
 
 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
-       { .fw_name = "bi_tcxo" },
+       { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
        { .hw = &gpu_cc_pll0.clkr.hw },
        { .hw = &gpu_cc_pll1.clkr.hw },
-       { .fw_name = "gcc_gpu_gpll0_clk" },
-       { .fw_name = "gcc_gpu_gpll0_div_clk" },
+       { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" },
+       { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" },
 };
 
 static const struct parent_map gpu_cc_parent_map_1[] = {
@@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = {
 };
 
 static const struct clk_parent_data gpu_cc_parent_data_1[] = {
-       { .fw_name = "bi_tcxo" },
+       { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
        { .hw = &crc_div.hw },
        { .hw = &gpu_cc_pll0.clkr.hw },
        { .hw = &gpu_cc_pll1.clkr.hw },
        { .hw = &gpu_cc_pll1.clkr.hw },
-       { .fw_name = "gcc_gpu_gpll0_clk" },
+       { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" },
 };
 
 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {