},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+ "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+ "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
"ScaleUnit": "100%"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
- },
- {
"BriefDescription": "This metric represents rate of split store accesses",
"MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
"MetricGroup": "TopdownL4;tma_store_bound_group",
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
+ "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #core_wide < 1 else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD) )",
+ "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "Page_Walks_Utilization"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
- "MetricGroup": "Mem;SoC",
- "MetricName": "MEM_Request_Latency"
- },
- {
- "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
- "MetricGroup": "Mem;SoC",
- "MetricName": "MEM_Parallel_Requests"
- },
- {
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
},
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "This event counts the total number of L2 code requests.",
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
},
{
"BriefDescription": "Demand requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Demand requests to L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
},
{
"BriefDescription": "All requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "All L2 requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
"UMask": "0x8"
},
{
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
},
{
"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70",
"EventCode": "0xD1",
},
{
"BriefDescription": "All retired load uops. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "BDM76",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.",
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
[
{
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
},
{
"BriefDescription": "Number of times HLE commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
},
{
"BriefDescription": "Loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above four.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above eight.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
},
{
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
},
{
"BriefDescription": "Number of times RTM commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
[
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken macro-conditional branch instructions.",
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired direct near calls.",
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all (macro) branch instructions retired.",
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
},
{
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
},
{
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
},
{
"BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
},
{
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "This event counts not taken branch instructions retired.",
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM61",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "BDM11, BDM55",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
},
{
"BriefDescription": "False dependencies in MOB due to partial compare",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
},
{
"BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
},
{
"BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
[
{
"BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_C_BOUNCE_CONTROL",
"PerPkg": "1",
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBO"
},
{
"BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
},
{
"BriefDescription": "FaST wire asserted",
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_C_FAST_ASSERTED",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; Any Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; Any Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.READ",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
},
{
"BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.I_STATE",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
},
{
"BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.NID",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
},
{
"BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.WC_ALIASING",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE0",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE1",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE2",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE3",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.LRU_DECREMENT",
"PerPkg": "1",
},
{
"BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
"PerPkg": "1",
},
{
"BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
},
{
"BriefDescription": "AD",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "AK",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AK",
"PerPkg": "1",
},
{
"BriefDescription": "BL",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "IV",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.IV",
"PerPkg": "1",
},
{
"BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.PRQ",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
"PerPkg": "1",
},
{
"BriefDescription": "Probe Queue Retries; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.NID",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
"PerPkg": "1",
},
{
"BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
"PerPkg": "1",
},
{
"BriefDescription": "SBo Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
},
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.BL_BOTH",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
},
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
},
{
"BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ALLOCS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.EVICTS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.INVALS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSP",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.WBMTOI",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
"PerPkg": "1",
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.INVALS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSP",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
"PerPkg": "1",
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
"EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
"EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS2",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS3",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
"PerPkg": "1",
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Cancelled",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.CANCELLED",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE_USEFUL",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "HA AK Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "HA BL Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
},
{
"BriefDescription": "Data beat the Snoop Responses; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Data beat the Snoop Responses; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles with Snoops Outstanding; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Cycles Not Empty; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Cycles Not Empty; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
"PerPkg": "1",
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; For AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.AK",
"PerPkg": "1",
},
{
"BriefDescription": "Injection Starvation; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
[
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
},
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
"Unit": "iMC"
},
{
+ "EventCode": "0x42",
+ "EventName": "UNC_M_POWER_PCU_THROTTLING",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
},
{
"BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
},
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
},
{
"BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; RFO",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_TIMEOUT",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Data Throttled",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
},
{
"BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
},
{
"BriefDescription": "Inbound Transaction Count; Write Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
"Unit": "R2PCIe"
},
{
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
+ {
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AD Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
},
{
"BriefDescription": "AK Ingress Bounced; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AK Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "R2 BL Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C State Residency - C1E",
- "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Package C7 State Residency",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
GenuineIntel-6-BE,v1.16,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core
-GenuineIntel-6-56,v23,broadwellde,core
+GenuineIntel-6-56,v7,broadwellde,core
GenuineIntel-6-4F,v19,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core
GenuineIntel-6-9[6C],v1.03,elkhartlake,core
projects / platform / kernel / linux-starfive.git / commitdiff