sim: mips: hoist "m16" igen rules up to common builds

diff --git a/sim/Makefile.in b/sim/Makefile.in
index 1c2dfc0..947814e 100644 (file)
--- a/sim/Makefile.in
+++ b/sim/Makefile.in
@@ -203,30 +203,36 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@     $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@     mips/stamp-gen-mode-single
 
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_63 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_63 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        mips/stamp-gen-mode-m16-m16 \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@        mips/stamp-gen-mode-m16-m32
+
 @SIM_ENABLE_ARCH_mips_TRUE@am__append_64 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_65 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_66 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_67 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_68 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_65 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_66 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_67 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_68 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
 @SIM_ENABLE_ARCH_mn10300_TRUE@am__append_69 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_70 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_71 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_72 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_73 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_70 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_71 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_72 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_73 = or1k/run
 @SIM_ENABLE_ARCH_or1k_TRUE@am__append_74 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_75 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_76 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_77 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_78 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_79 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_80 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_81 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_82 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_83 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_84 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_85 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_75 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_76 = ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_77 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_78 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_79 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_80 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_81 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_82 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_83 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_84 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_85 = v850/run
 @SIM_ENABLE_ARCH_v850_TRUE@am__append_86 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_87 = $(v850_BUILD_OUTPUTS)
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@@ -1205,22 +1211,22 @@ SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
 AM_MAKEFLAGS = SIM_NEW_COMMON_OBJS_="$(SIM_NEW_COMMON_OBJS)" \
        $(am__append_3) $(am__append_12) $(am__append_21) \
        $(am__append_42) $(am__append_50) $(am__append_54) \
-       $(am__append_61) $(am__append_67)
+       $(am__append_61) $(am__append_68)
 pkginclude_HEADERS = $(am__append_1)
 noinst_LIBRARIES = $(SIM_COMMON_LIB) $(am__append_5)
 CLEANFILES = common/version.c common/version.c-stamp \
        testsuite/common/bits-gen testsuite/common/bits32m0.c \
        testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
        testsuite/common/bits64m63.c
-DISTCLEANFILES = $(am__append_65)
+DISTCLEANFILES = $(am__append_66)
 MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
        %,%/stamp-hw,$(SIM_ENABLED_ARCHES)) $(am__append_7) \
        site-sim-config.exp testrun.log testrun.sum $(am__append_15) \
        $(am__append_19) $(am__append_24) $(am__append_28) \
        $(am__append_35) $(am__append_40) $(am__append_44) \
        $(am__append_48) $(am__append_52) $(am__append_57) \
-       $(am__append_64) $(am__append_69) $(am__append_74) \
-       $(am__append_83) $(am__append_86)
+       $(am__append_65) $(am__append_70) $(am__append_75) \
+       $(am__append_84) $(am__append_87)
 AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
 AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
        $(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
@@ -1234,8 +1240,8 @@ SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
        $(am__append_17) $(am__append_23) $(am__append_26) \
        $(am__append_34) $(am__append_39) $(am__append_43) \
        $(am__append_46) $(am__append_51) $(am__append_55) \
-       $(am__append_63) $(am__append_68) $(am__append_73) \
-       $(am__append_81) $(am__append_85)
+       $(am__append_64) $(am__append_69) $(am__append_74) \
+       $(am__append_82) $(am__append_86)
 SIM_INSTALL_DATA_LOCAL_DEPS = 
 SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_30)
 SIM_UNINSTALL_LOCAL_DEPS = $(am__append_31)
@@ -1610,10 +1616,33 @@ testsuite_common_CPPFLAGS = \
 @SIM_ENABLE_ARCH_mips_TRUE@    mips/engine.c \
 @SIM_ENABLE_ARCH_mips_TRUE@    mips/irun.c
 
+@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_icache.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_icache.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_idecode.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_idecode.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_semantics.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_semantics.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_model.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_model.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_support.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m16_support.c \
+@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_icache.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_icache.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_idecode.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_idecode.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_semantics.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_semantics.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_model.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_model.c \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_support.h \
+@SIM_ENABLE_ARCH_mips_TRUE@    mips/m32_support.c
+
 @SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS =  \
 @SIM_ENABLE_ARCH_mips_TRUE@    $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
 @SIM_ENABLE_ARCH_mips_TRUE@    mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_62)
+@SIM_ENABLE_ARCH_mips_TRUE@    $(am__append_62) $(am__append_63)
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@@ -1632,6 +1661,7 @@ testsuite_common_CPPFLAGS = \
 @SIM_ENABLE_ARCH_mips_TRUE@    mips/vr.igen
 
 @SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc
+@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
 @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES = 
 @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
 @SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \
@@ -3558,6 +3588,8 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
 
 @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable
 @SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE): mips/stamp-gen-mode-single
+@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16): mips/stamp-gen-mode-m16-m16
+@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32): mips/stamp-gen-mode-m16-m32
 
 @SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-igen-itable: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(IGEN)
 @SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_GEN)$(IGEN_RUN) \
@@ -3604,6 +3636,60 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
 @SIM_ENABLE_ARCH_mips_TRUE@            -n irun.c      -r  mips/irun.c
 @SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_at)touch $@
 
+@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m16: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_M16_DC) $(IGEN)
+@SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_GEN)$(IGEN_RUN) \
+@SIM_ENABLE_ARCH_mips_TRUE@            $(mips_IGEN_TRACE) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -I $(srcdir)/mips \
+@SIM_ENABLE_ARCH_mips_TRUE@            -Werror \
+@SIM_ENABLE_ARCH_mips_TRUE@            -Wnodiscard \
+@SIM_ENABLE_ARCH_mips_TRUE@            $(SIM_MIPS_M16_FLAGS) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -G gen-direct-access \
+@SIM_ENABLE_ARCH_mips_TRUE@            -G gen-zero-r0 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -B 16 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -H 15 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -i $(mips_IGEN_INSN) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -o $(mips_M16_DC) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -P m16_ \
+@SIM_ENABLE_ARCH_mips_TRUE@            -x \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_icache.h    -hc mips/m16_icache.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_icache.c    -c  mips/m16_icache.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_semantics.h -hs mips/m16_semantics.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_semantics.c -s  mips/m16_semantics.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_idecode.h   -hd mips/m16_idecode.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_idecode.c   -d  mips/m16_idecode.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_model.h     -hm mips/m16_model.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_model.c     -m  mips/m16_model.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_support.h   -hf mips/m16_support.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m16_support.c   -f  mips/m16_support.c
+@SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_at)touch $@
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m32: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN)
+@SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_GEN)$(IGEN_RUN) \
+@SIM_ENABLE_ARCH_mips_TRUE@            $(mips_IGEN_TRACE) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -I $(srcdir)/mips \
+@SIM_ENABLE_ARCH_mips_TRUE@            -Werror \
+@SIM_ENABLE_ARCH_mips_TRUE@            -Wnodiscard \
+@SIM_ENABLE_ARCH_mips_TRUE@            $(SIM_MIPS_SINGLE_FLAGS) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -G gen-direct-access \
+@SIM_ENABLE_ARCH_mips_TRUE@            -G gen-zero-r0 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -B 32 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -H 31 \
+@SIM_ENABLE_ARCH_mips_TRUE@            -i $(mips_IGEN_INSN) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -o $(mips_IGEN_DC) \
+@SIM_ENABLE_ARCH_mips_TRUE@            -P m32_ \
+@SIM_ENABLE_ARCH_mips_TRUE@            -x \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_icache.h    -hc mips/m32_icache.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_icache.c    -c  mips/m32_icache.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_semantics.h -hs mips/m32_semantics.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_semantics.c -s  mips/m32_semantics.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_idecode.h   -hd mips/m32_idecode.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_idecode.c   -d  mips/m32_idecode.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_model.h     -hm mips/m32_model.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_model.c     -m  mips/m32_model.c \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_support.h   -hf mips/m32_support.h \
+@SIM_ENABLE_ARCH_mips_TRUE@            -n m32_support.c   -f  mips/m32_support.c
+@SIM_ENABLE_ARCH_mips_TRUE@    $(AM_V_at)touch $@
+
 @SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen
 @SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/stamp-igen: $(mn10300_IGEN_INSN) $(mn10300_IGEN_INSN_INC) $(mn10300_IGEN_DC) $(IGEN)
 @SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \

diff --git a/sim/configure b/sim/configure
index 66e6cda..ef6cc0a 100755 (executable)
--- a/sim/configure
+++ b/sim/configure
@@ -641,6 +641,8 @@ LTLIBOBJS
 include_makefile
 SIM_RX_CYCLE_ACCURATE_FLAGS
 SIM_RISCV_BITSIZE
+SIM_MIPS_GEN_MODE_M16_FALSE
+SIM_MIPS_GEN_MODE_M16_TRUE
 SIM_MIPS_GEN_MODE_SINGLE_FALSE
 SIM_MIPS_GEN_MODE_SINGLE_TRUE
 SIM_MIPS_MULTI_OBJ
@@ -12446,7 +12448,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12449 "configure"
+#line 12451 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -12552,7 +12554,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 12555 "configure"
+#line 12557 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -16626,6 +16628,14 @@ else
   SIM_MIPS_GEN_MODE_SINGLE_FALSE=
 fi
 
+ if test "$SIM_MIPS_GEN" = "M16"; then
+  SIM_MIPS_GEN_MODE_M16_TRUE=
+  SIM_MIPS_GEN_MODE_M16_FALSE='#'
+else
+  SIM_MIPS_GEN_MODE_M16_TRUE='#'
+  SIM_MIPS_GEN_MODE_M16_FALSE=
+fi
+
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking riscv bitsize" >&5
 $as_echo_n "checking riscv bitsize... " >&6; }
@@ -16948,6 +16958,10 @@ if test -z "${SIM_MIPS_GEN_MODE_SINGLE_TRUE}" && test -z "${SIM_MIPS_GEN_MODE_SI
   as_fn_error $? "conditional \"SIM_MIPS_GEN_MODE_SINGLE\" was never defined.
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
+if test -z "${SIM_MIPS_GEN_MODE_M16_TRUE}" && test -z "${SIM_MIPS_GEN_MODE_M16_FALSE}"; then
+  as_fn_error $? "conditional \"SIM_MIPS_GEN_MODE_M16\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
 
 : "${CONFIG_STATUS=./config.status}"
 ac_write_fail=0

diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
index 247208f..15016f9 100644 (file)
--- a/sim/mips/Makefile.in
+++ b/sim/mips/Makefile.in
@@ -3,8 +3,6 @@
 
 ## COMMON_PRE_CONFIG_FRAG
 
-SIM_MIPS_SINGLE_FLAGS = @SIM_MIPS_SINGLE_FLAGS@
-SIM_MIPS_M16_FLAGS = @SIM_MIPS_M16_FLAGS@
 SIM_MIPS_GEN = @SIM_MIPS_GEN@
 SIM_MIPS_MULTI_IGEN_CONFIGS = @SIM_MIPS_MULTI_IGEN_CONFIGS@
 SIM_MIPS_MULTI_SRC = @SIM_MIPS_MULTI_SRC@
@@ -87,87 +85,9 @@ IGEN_INCLUDE=\
        $(srcdir)/mips3264r6.igen \
 
 SIM_SINGLE_ALL =
-SIM_M16_ALL = tmp-m16
+SIM_M16_ALL =
 SIM_MULTI_ALL = tmp-multi
 
-BUILT_SRC_FROM_M16 = \
-       m16_icache.h \
-       m16_icache.c \
-       m16_idecode.h \
-       m16_idecode.c \
-       m16_semantics.h \
-       m16_semantics.c \
-       m16_model.h \
-       m16_model.c \
-       m16_support.h \
-       m16_support.c \
-       \
-       m32_icache.h \
-       m32_icache.c \
-       m32_idecode.h \
-       m32_idecode.c \
-       m32_semantics.h \
-       m32_semantics.c \
-       m32_model.h \
-       m32_model.c \
-       m32_support.h \
-       m32_support.c \
-
-$(BUILT_SRC_FROM_M16): tmp-m16
-
-tmp-m16: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE)
-       $(ECHO_IGEN) $(IGEN_RUN) \
-               $(IGEN_TRACE) \
-               -I $(srcdir) \
-               -Werror \
-               -Wnodiscard \
-               $(SIM_MIPS_M16_FLAGS) \
-               -G gen-direct-access \
-               -G gen-zero-r0 \
-               -B 16 \
-               -H 15 \
-               -i $(IGEN_INSN) \
-               -o $(M16_DC) \
-               -P m16_ \
-               -x \
-               -n m16_icache.h    -hc m16_icache.h \
-               -n m16_icache.c    -c  m16_icache.c \
-               -n m16_semantics.h -hs m16_semantics.h \
-               -n m16_semantics.c -s  m16_semantics.c \
-               -n m16_idecode.h   -hd m16_idecode.h \
-               -n m16_idecode.c   -d  m16_idecode.c \
-               -n m16_model.h     -hm m16_model.h \
-               -n m16_model.c     -m  m16_model.c \
-               -n m16_support.h   -hf m16_support.h \
-               -n m16_support.c   -f  m16_support.c \
-               #
-       $(ECHO_IGEN) $(IGEN_RUN) \
-               $(IGEN_TRACE) \
-               -I $(srcdir) \
-               -Werror \
-               -Wnodiscard \
-               $(SIM_MIPS_SINGLE_FLAGS) \
-               -G gen-direct-access \
-               -G gen-zero-r0 \
-               -B 32 \
-               -H 31 \
-               -i $(IGEN_INSN) \
-               -o $(IGEN_DC) \
-               -P m32_ \
-               -x \
-               -n m32_icache.h    -hc m32_icache.h \
-               -n m32_icache.c    -c  m32_icache.c \
-               -n m32_semantics.h -hs m32_semantics.h \
-               -n m32_semantics.c -s  m32_semantics.c \
-               -n m32_idecode.h   -hd m32_idecode.h \
-               -n m32_idecode.c   -d  m32_idecode.c \
-               -n m32_model.h     -hm m32_model.h \
-               -n m32_model.c     -m  m32_model.c \
-               -n m32_support.h   -hf m32_support.h \
-               -n m32_support.c   -f  m32_support.c \
-               #
-       $(SILENCE) touch $@
-
 BUILT_SRC_FROM_MULTI = $(SIM_MIPS_MULTI_SRC)
 
 $(BUILT_SRC_FROM_MULTI): tmp-multi
@@ -257,7 +177,6 @@ tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c
        $(SILENCE) touch $@
 
 clean-extra:
-       rm -f $(BUILT_SRC_FROM_M16)
        rm -f $(BUILT_SRC_FROM_MULTI)
        rm -f tmp-*
        rm -f micromips16*.o micromips32*.o m16*.o m32*.o

diff --git a/sim/mips/acinclude.m4 b/sim/mips/acinclude.m4
index 313e40b..efabd27 100644 (file)
--- a/sim/mips/acinclude.m4
+++ b/sim/mips/acinclude.m4
@@ -334,3 +334,4 @@ AC_SUBST(SIM_MIPS_MULTI_IGEN_CONFIGS)
 AC_SUBST(SIM_MIPS_MULTI_SRC)
 AC_SUBST(SIM_MIPS_MULTI_OBJ)
 AM_CONDITIONAL([SIM_MIPS_GEN_MODE_SINGLE], [test "$SIM_MIPS_GEN" = "SINGLE"])
+AM_CONDITIONAL([SIM_MIPS_GEN_MODE_M16], [test "$SIM_MIPS_GEN" = "M16"])

diff --git a/sim/mips/local.mk b/sim/mips/local.mk
index 0a6f1da..b6e482e 100644 (file)
--- a/sim/mips/local.mk
+++ b/sim/mips/local.mk
@@ -44,6 +44,28 @@ AM_MAKEFLAGS += %C%_SIM_EXTRA_HW_DEVICES="$(%C%_SIM_EXTRA_HW_DEVICES)"
        %D%/engine.h \
        %D%/engine.c \
        %D%/irun.c
+%C%_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \
+       %D%/m16_icache.h \
+       %D%/m16_icache.c \
+       %D%/m16_idecode.h \
+       %D%/m16_idecode.c \
+       %D%/m16_semantics.h \
+       %D%/m16_semantics.c \
+       %D%/m16_model.h \
+       %D%/m16_model.c \
+       %D%/m16_support.h \
+       %D%/m16_support.c \
+%C%_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \
+       %D%/m32_icache.h \
+       %D%/m32_icache.c \
+       %D%/m32_idecode.h \
+       %D%/m32_idecode.c \
+       %D%/m32_semantics.h \
+       %D%/m32_semantics.c \
+       %D%/m32_model.h \
+       %D%/m32_model.c \
+       %D%/m32_support.h \
+       %D%/m32_support.c
 %C%_BUILD_OUTPUTS = \
        $(%C%_BUILT_SRC_FROM_IGEN_ITABLE) \
        %D%/stamp-igen-itable
@@ -52,12 +74,21 @@ if SIM_MIPS_GEN_MODE_SINGLE
        $(%C%_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
        %D%/stamp-gen-mode-single
 endif
+if SIM_MIPS_GEN_MODE_M16
+%C%_BUILD_OUTPUTS += \
+       $(%C%_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
+       $(%C%_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
+       %D%/stamp-gen-mode-m16-m16 \
+       %D%/stamp-gen-mode-m16-m32
+endif
 
 ## This makes sure build tools are available before building the arch-subdirs.
 SIM_ALL_RECURSIVE_DEPS += $(%C%_BUILD_OUTPUTS)
 
 $(%C%_BUILT_SRC_FROM_IGEN_ITABLE): %D%/stamp-igen-itable
 $(%C%_BUILT_SRC_FROM_GEN_MODE_SINGLE): %D%/stamp-gen-mode-single
+$(%C%_BUILT_SRC_FROM_GEN_MODE_M16_M16): %D%/stamp-gen-mode-m16-m16
+$(%C%_BUILT_SRC_FROM_GEN_MODE_M16_M32): %D%/stamp-gen-mode-m16-m32
 
 %C%_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
 %C%_IGEN_INSN = $(srcdir)/%D%/mips.igen
@@ -76,6 +107,7 @@ $(%C%_BUILT_SRC_FROM_GEN_MODE_SINGLE): %D%/stamp-gen-mode-single
        %D%/tx.igen \
        %D%/vr.igen
 %C%_IGEN_DC = $(srcdir)/%D%/mips.dc
+%C%_M16_DC = $(srcdir)/%D%/m16.dc
 
 ## NB: Since these can be built by a number of generators, care
 ##     must be taken to ensure that they are only dependant on
@@ -125,6 +157,60 @@ $(%C%_BUILT_SRC_FROM_GEN_MODE_SINGLE): %D%/stamp-gen-mode-single
                -n irun.c      -r  %D%/irun.c
        $(AM_V_at)touch $@
 
+%D%/stamp-gen-mode-m16-m16: $(%C%_IGEN_INSN) $(%C%_IGEN_INSN_INC) $(%C%_M16_DC) $(IGEN)
+       $(AM_V_GEN)$(IGEN_RUN) \
+               $(%C%_IGEN_TRACE) \
+               -I $(srcdir)/%D% \
+               -Werror \
+               -Wnodiscard \
+               $(SIM_MIPS_M16_FLAGS) \
+               -G gen-direct-access \
+               -G gen-zero-r0 \
+               -B 16 \
+               -H 15 \
+               -i $(%C%_IGEN_INSN) \
+               -o $(%C%_M16_DC) \
+               -P m16_ \
+               -x \
+               -n m16_icache.h    -hc %D%/m16_icache.h \
+               -n m16_icache.c    -c  %D%/m16_icache.c \
+               -n m16_semantics.h -hs %D%/m16_semantics.h \
+               -n m16_semantics.c -s  %D%/m16_semantics.c \
+               -n m16_idecode.h   -hd %D%/m16_idecode.h \
+               -n m16_idecode.c   -d  %D%/m16_idecode.c \
+               -n m16_model.h     -hm %D%/m16_model.h \
+               -n m16_model.c     -m  %D%/m16_model.c \
+               -n m16_support.h   -hf %D%/m16_support.h \
+               -n m16_support.c   -f  %D%/m16_support.c
+       $(AM_V_at)touch $@
+
+%D%/stamp-gen-mode-m16-m32: $(%C%_IGEN_INSN) $(%C%_IGEN_INSN_INC) $(%C%_IGEN_DC) $(IGEN)
+       $(AM_V_GEN)$(IGEN_RUN) \
+               $(%C%_IGEN_TRACE) \
+               -I $(srcdir)/%D% \
+               -Werror \
+               -Wnodiscard \
+               $(SIM_MIPS_SINGLE_FLAGS) \
+               -G gen-direct-access \
+               -G gen-zero-r0 \
+               -B 32 \
+               -H 31 \
+               -i $(%C%_IGEN_INSN) \
+               -o $(%C%_IGEN_DC) \
+               -P m32_ \
+               -x \
+               -n m32_icache.h    -hc %D%/m32_icache.h \
+               -n m32_icache.c    -c  %D%/m32_icache.c \
+               -n m32_semantics.h -hs %D%/m32_semantics.h \
+               -n m32_semantics.c -s  %D%/m32_semantics.c \
+               -n m32_idecode.h   -hd %D%/m32_idecode.h \
+               -n m32_idecode.c   -d  %D%/m32_idecode.c \
+               -n m32_model.h     -hm %D%/m32_model.h \
+               -n m32_model.c     -m  %D%/m32_model.c \
+               -n m32_support.h   -hf %D%/m32_support.h \
+               -n m32_support.c   -f  %D%/m32_support.c
+       $(AM_V_at)touch $@
+
 MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
 ## These are created by mips/acinclude.m4 during configure time.
 DISTCLEANFILES += %D%/multi-include.h %D%/multi-run.c