drm/amd/display: Add debug flag for VSR support

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index eeb8ee5..defc443 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -218,6 +218,7 @@ struct dc_debug {
        bool disable_hbup_pg;
        bool disable_dpp_pg;
        bool stereo_support;
+       bool vsr_support;
 };
 struct dc_state;
 struct resource_pool;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 3000dda..1b108ae 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -428,6 +428,7 @@ static const struct dc_debug debug_defaults_drv = {
                .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
                .disable_dcc = DCC_ENABLE,
                .voltage_align_fclk = true,
+               .vsr_support = true,
 };
 
 static const struct dc_debug debug_defaults_diags = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 8dbc82f..178dadd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -25,6 +25,7 @@
 
 #include "reg_helper.h"
 #include "dcn10_timing_generator.h"
+#include "dc.h"
 
 #define REG(reg)\
        tgn10->tg_regs->reg